Two-transistor zero-power electrically-alterable non-volatile la

Details Two-transistor zero-power electrically-alterable non-volatile la Two-transistor zero-power electrically-alterable non-volatile la

1995-01-06

1996-12-24

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257320, 257321, H01L 29788

Patent

active

055876030

ABSTRACT:
A two-transistor, zero-power, electrically-alterable non-volatile latch element comprises an input node, an output node, and an erase node. A P-Channel MOS transistor has a source connected to a source of first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate. An N-Channel MOS transistor has a source connected to a source of second electrical potential lower than the first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate and electrically connected to the floating gate of the P-Channel MOS transistor. The floating gates of the P-Channel MOS transistor and the N-Channel MOS transistor are capacitively coupled to the erase node via a tunnel dielectric.

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