Two transistor ferroelectric memory cell

Details Two transistor ferroelectric memory cell Two transistor ferroelectric memory cell

1997-06-06

1999-08-03

Tsai, Jey

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257300, H01L 218242

Patent

active

059329041

ABSTRACT:
The method of forming the two transistor semi-conductor structure includes forming a device area for a MOS transistor and for a ferroelectric memory (FEM) gate unit on a silicon substrate. A conventional MOS transistor is formed on the substrate. A FEM cell includes a FEM gate unit formed on the substrate, either above or along side of the MOS transistor. The FEM gate unit is spaced apart from a source region and a drain region. Formation of the various conductive channels may take place at various stages of the manufacture, depending on what other devices are built on the substrate, and depending on the efficiencies of the various orders of construction. The structure of the two transistor semiconductor includes a silicon substrate, which may be a bulk silicon substrate or an SOI-type substrate. Conductive channels of three types are located above the substrate. A FEM gate unit is located above a gate region, either over or along side of a conventional MOS transistor, wherein the FEM gate unit includes a lower metal layer, an FE layer, and an upper metal layer.

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