Two transistor EEPROM cell

Details Two transistor EEPROM cell Two transistor EEPROM cell

1999-02-05

2001-09-25

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000, C257S318000, C438S259000, C438S264000

Reexamination Certificate

active

06294811

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to an electrically erasable programmable read only memory (“EEPROM”) cell.
2. Description of Related Art
The semiconductor community faces increasingly difficult challenges as it moves into production of semiconductor devices at feature sizes approaching 0.1 micron. Cell designs for typical semiconductor devices must be made more reliable, scalable, cost effective to manufacture and able to operate at lower power in order for manufacturers to compete in the semiconductor industry. EEPROM devices are one such device that must meet these challenges.
EEPROM devices are generally known as read-only memory in which the memory cells that store information may be erased and reprogrammed electrically. An EEPROM cell is typically made up of three separate transistors, namely, a write transistor, a sense transistor and a read transistor. The EEPROM cell is able to be programmed, erased and read by removing or adding electrons to a floating gate. Thus, in one example, the floating gate is programmed by removing free electrons from the floating gate and thereby giving the floating gate a positive charge. When it is desired to erase the EEPROM cell in this example, the floating gate is given a net negative charge by injecting electrons onto the floating gate. The read operation is performed by reading the state (current) of the sense transistor. In order to give the floating gate a positive charge (program) or negative charge (erase), electron tunneling, for example using the well-known Fowler-Nordheim tunneling technique, may be performed by applying the appropriate voltage potentials between the floating gate and a region, such as a drain region, of a transistor. Upon applying the appropriate voltage potentials, electron tunneling occurs through a tunnel oxide layer between the floating gate and the region.
As the feature sizes of EEPROM cells are scaled downward, the prior art EEPROM cells exhibit certain scaleablity, cost and reliability limitations. First, since three transistors (write, sense and read) form the typical EEPROM cell, the size of the EEPROM cell is large. Also, with a three-transistor cell, three oxide layers (typically two gate oxide layers and one tunnel oxide layer) are needed that may vary in thicknesses requiring complex process steps to form the oxide layers of varying thicknesses. Second, the manufacturing process for a smaller EEPROM cell becomes more complex and, accordingly, manufacturing costs rise as transistor channel lengths are reduced. For example, as the channel length of a transistor of the EEPROM cell is scaled downward, the thickness of the gate oxide overlying the channel must also be reduced since the gate oxide thickness must be scaled with the channel length. In view of the fact that EEPROM cells already have a complex process to form multiple oxide thicknesses, additional oxide thicknesses for the transistors would add additional steps to further complicate the manufacturing process and thereby increase manufacturing costs.
In addition to this scaling problem, reliability problems also exist with previous EEPROM cells. First, the EEPROM cell is typically both programmed and erased through one tunnel oxide window of a transistor region that may deteriorate the cell quickly. In general, the tunnel oxide window deteriorates after tens of thousands of program/erase cycles and that deterioration cycle is shortened by only using the tunnel oxide window for both programming and erasing operations. Thus, the use of the window for both programming and erasing of the EEPROM cell causes the cell to be significantly less reliable. A further reliability limitation of previous EEPROM cells is that the tunnel oxide window is less reliable because it is formed over a highly doped program junction (PRJ). The high doping concentration of the PRJ degrades the surface immediately above the PRJ and thereby reduces the EEPROM cell's reliability. A still further limitation of the EEPROM cell is that the voltages needed to program, erase and read the cell are high due to the relatively large feature sizes of the cell. Thus, in order to achieve lower voltages to operate the EEPROM cell, feature sizes of the cell must be scaled downward.
Thus, a need exists for a redesigned EEPROM cell that (1) does not add costly steps to the manufacturing process, (2) does not suffer from reliability problems caused by both programing and erasing through one tunnel oxide window, (3) does not deteriorate through use of a PRJ oxide and (4) operates at a lower power by using smaller feature sizes.
SUMMARY OF THE INVENTION
A two transistor EEPROM cell is described that is erased by electron tunneling across an entire portion of a tunneling channel and programmed by electron tunneling at an edge of a tunneling drain. The EEPROM cell has two transistors formed in a semiconductor substrate: a tunneling transistor and a read transistor. The tunneling transistor has a tunneling source, a tunneling drain, and a tunneling channel between the tunneling source and the tunneling drain. The tunneling source and the tunneling drain have a second conductivity type that is opposite the first conductivity type of the semiconductor substrate. A tunnel oxide layer is formed over the tunneling channel, the tunneling source and the tunneling drain. A program junction region having the second conductivity type is formed in the semiconductor substrate and is separated from the tunneling transistor by a field oxide region. The read transistor, also formed in the semiconductor substrate, is electrically connected to the tunneling transistor through the tunneling drain. A floating gate overlies the tunnel oxide layer and the program junction oxide layer. Electron tunneling occurs through the tunnel oxide layer overlying an edge of the tunneling drain upon incurrence of a sufficient voltage potential between the floating gate and the tunneling drain to program the EEPROM cell. Electron tunneling also occurs through the tunnel oxide layer overlying the tunneling channel upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel to erase the EEPROM cell.
The EEPROM cell is a two transistor cell which is smaller than previous three transistor cells. The EEPROM cell of the present invention provides electron tunneling through the tunnel oxide layer overlying the tunneling channel to occur across the entire portion of the tunneling channel to erase the EEPROM cell, thereby increasing the EEPROM cell reliability. Also, the EEPROM cell is programmed by electron tunneling through the tunnel oxide layer overlying an edge of the tunneling drain, while the erase operation is performed across a tunnel channel. Thus, the programming and erasing operations are separated across different regions (edge of the tunneling drain and the entire tunneling channel) which increases the EEPROM cell's reliability. The EEPROM cell further has reduced thicknesses for the tunnel oxide layer and the program junction oxide layer to improve scaleablity and reduce operating voltages of the EEPROM cell of the present invention. The EEPROM cell further has a reduced third oxide thickness in the periphery of an integrated circuit containing the EEPROM cell of the present invention that further lowers the voltages needed to operate the integrated circuit.


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