Two-transistor dram cell with high alpha particle immunity

Static information storage and retrieval – Magnetic bubbles – Guide structure

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357 55, 357 41, 365185, H01L 2978, H01L 2906, H01L 2702, G11C 1134

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048643742

ABSTRACT:
A DRAM cell (8) having a storage node (18), a pass transistor (76) and a polysilicon word line (84) formed within an oxide isolated trench (68), thereby providing high soft error immunity. A write bit line (66) functions as the drain region (78) of the pass transistor (76) and is isolated from the substrate by a oxide isolation (64), thereby enhancing soft error immunity. The trench (68) includes an annular opening for providing intimate contact between the past transistor conduction channel (82) and the single crystal silicon substrate (36). During processing, the polysilicon conduction channel (82) of the pass transistor (76) is converted into single crystal silicon, thereby providing enhanced performance of the cell (8).

REFERENCES:
patent: 4432006 (1984-02-01), Takei
patent: 4448400 (1984-05-01), Harari
patent: 4716548 (1987-12-01), Mochizuki
patent: 4763181 (1988-08-01), Tasch, Jr.
Shichijo et al., "TITE RAM: A New SOI DRAM Gain Cell for Mbit DRAM's", Extended Abstracts of the 16th (1984 International) Conference on Solid State Devices and Materials, Kobe, 1984, pp. 265-268.

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