Two transistor DRAM cell and array

Details Two transistor DRAM cell and array Two transistor DRAM cell and array

1985-07-19

1987-11-03

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

357 236, G11C 1124

Patent

active

047047054

ABSTRACT:
A two transistor Dynamic Random Access Memory Cell and Array. Use of two pass transistors in series for the cell provides numerous additional capabilities for the DRAM array, and, in the preferred embodiment, provides bitline segment multiplexing, so that the sense amplifier pitch can be increased while the bitline capacitance as seen by the sense amplifier and by the memory cell is reduced. To accomplish this, the parasitic capacitance of the node between the two series pass transistors is kept to a minimum.

REFERENCES:
patent: 4086662 (1978-04-01), Itoh
patent: 4432072 (1984-02-01), Chao et al.
patent: 4577395 (1986-03-01), Shibata
W. Fischer, "One-Transistor-Cell Memory with Reduced Reference Cell Size", IBM Technical Disclosure Bulletin, vol. 20, No. 4, Sep. 1977, pp. 1501-1502.

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