Two transistor dram cell

Details Two transistor dram cell Two transistor dram cell

1991-10-30

1992-06-16

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365150, 365174, 365182, 36518909, G11C 702

Patent

active

051229862

ABSTRACT:
A semiconductor memory cell includes a write row line, a read row line, a write column line, a read column line, a single MOS write transistor, and a single MOS read transistor. The write transistor has a first controlled node coupled to the write column line, a second controlled node, and a gate coupled to the write row line. The read transistor has a first controlled node coupled to the read column line, a second controlled node coupled to the read row line, and a gate coupled to the second controlled node to define a charge storage node.

REFERENCES:
patent: 3614749 (1971-10-01), Radcliffe
patent: 4627031 (1986-12-01), Van Tran
patent: 4636988 (1987-01-01), Van Tran
patent: 4823319 (1989-04-01), Pfennings
patent: 5018106 (1991-05-01), Ul Haq et al.
R. Feryszka et al., "Two Transistor Dynamic Memory Cell," RCA Tech. Notes, #TN1007, Apr. 9, 1975, 1,2.

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