Two-tiered dynamic random access memory (DRAM) cell

Details Two-tiered dynamic random access memory (DRAM) cell Two-tiered dynamic random access memory (DRAM) cell

1985-09-20

1987-05-26

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Semiconductive

365189, 357 237, G11C 1134

Patent

active

046690620

ABSTRACT:
A dynamic random access memory (DRAM) cell has three MIS transistors arranged in a two-tiered structure with high packing density. A read select MIS transistor has source, drain and channel regions formed in the substrate and is covered by a first insulating layer and a semiconductor layer. A write select MIS transistor has source and drain regions formed in the semiconducting layer, the first insulating layer having a contact window therein through which the drain regions of the write select and read select MIS transistors are connected. A storage MIS transistor has source, channel and drain regions formed in the substrate, the channel region of the storage MIS transistor comprising the source region of the read select MIS transistor and the drain region of the storage MIS transistor comprising the channel region of the read select MIS transistor, the respective channel regions of the read and storage MIS transistors being formed in a common level in the silicon substrate and directly connected therein between the source region of the storage MIS transistor and the drain region of the read select MIS transistor. The write select MIS transistor further may comprise a separate gate electrode, the gate electrodes of the write and read MIS transistors comprising portions of corresponding, separate conducting lines serving as write select and read select lines, respectively.

REFERENCES:
patent: 4476475 (1984-10-01), Naem et al.
patent: 4487635 (1984-12-01), Kugimiya et al.

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