Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-04-03
2002-01-01
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000, C326S081000, C326S056000, C327S309000
Reexamination Certificate
active
06335637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the field of integrated circuits. In particular, this invention relates to power supplies for integrated circuits and to an improved and simplified method for providing a stable source of power for a complementary metal oxide semiconductor (CMOS) integrated circuit utilizing a split-rail or dual power supply.
2. Related Art
The field of integrated circuitry is a rapidly developing field of technology. Integrated circuits are continually being made smaller with the attendant requirements of increasing both device speed and circuit density. The miniaturized devices built within and upon a semiconductor substrate are spaced very closely together and the integrated circuit density, that is, the number of integrated circuits per unit of surface area, continues to increase significantly. The highest integrated circuit density is achieved using Field Effect Transistors (FETs). A FET is a device having a source, gate, and drain arranged such that when a high logic signal voltage is applied to the gate, current may pass from the source to the drain. Similarly, the FET does not allow current to pass between the source and the drain when a low logic signal is applied to the gate.
As the integrated circuit density increases, the amount of power dissipated by the integrated circuits on the substrate increases proportionally. The amount of power dissipation is a concern because complicated heat sinks and circuit packaging may be required to prevent the chip temperature from rising above its rated operational temperature limit. Further, many devices containing integrated circuits typically operate on stored power. One example is a portable computer operating on battery power. As power dissipation increases, battery life decreases, and the shorter the operational life of the electronic device. Therefore, reducing the power consumption for a given integrated circuit density is important to the design of integrated circuits.
One way to decrease this power consumption is to reduce the voltage at which the circuits operate. However, decreasing the operational voltage level creates a compatibility problem because some integrated circuits are designed to operate at predetermined, specific voltage levels. For example, some circuits may interface with low voltage circuits, and these same circuits may need to operate at higher voltage levels to operate electromechanical devices. Also, there are many existing integrated circuits that cannot have their operating voltage altered, yet, new, lower voltage circuits must interact with them. Therefore, to lower the voltage of integrated circuits to dissipate less power, and still permit interaction with different existing hardware, some form of interface circuit is required.
In general, the related art has provided a variety of interface circuits for translating lower voltage levels into higher voltage logic levels and vice versa. This is because the logic voltage levels implemented in integrated circuits have been generally decreasing.
Many complementary metal oxide semiconductor (CMOS) integrated circuits require more than one power supply per chip. Such designs are known in the art as “split rail designs.” For instance, a split rail design is utilized when the internal or core chip voltage, VDD, operates at a different voltage level than the input/output (I/O) interface voltage or output driver voltage, OVDD. The integrated circuit core voltage, VDD, is limited by the integrated circuit technology or power dissipation requirements of the chip and the driver output voltage, OVDD.
Split rail designs create many challenges that must be addressed by both integrated circuit designers and system designers. For a typical split rail integrated circuit to operate properly, both of the power supplies must be in the powered up state. Numerous problems can occur when one supply is off while the other is on. Problems can also occur when the sequence in which the two supplies are powered up or powered down becomes critical.
One example of such a problem occurs when the integrated circuit core voltage, VDD, is in an off state and the output drivers are powered up via the output driver voltage, OVDD. In this situation, the output drivers will have lost all the control signals from the integrated circuit core which are derived from the integrated circuit core voltage, VDD. With no control signals to the drivers, the driver' output stages may try to pull the output pad both up and down at the same time. This scenario is characterized by a high crossover current effect from the output driver voltage, OVDD, to ground, which can be multiplied by hundreds of drivers throughout the chip thereby causing permanent equipment damage.
SUMMARY OF THE INVENTION
The present invention solves these problems in the related art by detecting the state of the core voltage and disabling the output drivers when the core voltage is detected to be off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing requirements. The disclosed invention also protects against the sudden loss of the integrated circuit core voltage power supply, VDD, during normal operation.
It is therefore an advantage of the present invention to provide a semiconductor chip comprising: a first plurality of circuits connected to a first voltage contact and a ground contact; a second plurality of circuits connected to a second voltage contact and said ground contact; a disabling circuit connected to said first voltage contact and said second voltage contact, and having an output node, said disabling circuit adapted to operate by pulling said output node to said ground contact only when a second voltage source is connected to said second voltage contact and no voltage source is connected to said first voltage contact; and wherein at least one of said second plurality of circuits is connected to said output node of said disabling circuit and wherein said at least one of said second plurality of circuits is adapted to enter a high impedance state when said output node is pulled to said ground contact.
Another aspect of the invention is to provide a method of protecting circuitry in a semiconductor chip, comprising: providing a first plurality of circuits connected to a first voltage contact and a ground contact; providing a second plurality of circuits connected to a second voltage contact and said ground contact; providing a disabling circuit connected to said first voltage contact and said second voltage contact, and having an output node, said disabling circuit operating by forcing said output node to said ground contact only when a second voltage source is connected to said second voltage contact and no voltage source is connected to said first voltage contact; connecting at least one of said second plurality of circuits to said output node of said disabling circuit.
The foregoing and other objects, features and advantages of the invention will be apparent in the following and more particular description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
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Correale, Jr. Anthony
Coughlin, Jr. Terry C.
Stout David W.
Paik Steven S.
Pivnichny John R.
Schmeiser Olsen & Watts
Tokar Michael
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