Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-02-21
2006-02-21
Gurley, Lynne A. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C438S636000, C438S637000, C438S638000, C438S643000, C438S666000, C438S700000
Reexamination Certificate
active
07001836
ABSTRACT:
A process for defining a dual damascene opening in a stack of insulator layers to expose a portion of a top surface of an underlying conductive structure, has been developed. The process features a two step procedure for removal of insulator stop layers, wherein the stop layers are employed to allow selective dry etch procedures to be used for definition of both the via opening component and the trench shape component of the dual damascene opening. After definition of the via opening, terminating at the top surface of an underlying, first silicon nitride stop layer, a photoresist shape is used as an etch mask to allow a dry etch procedure to define a trench shape in a top portion of an insulator stack, with the dry etch procedure terminating at the top surface of an overlying second silicon nitride stop layer. The dry etch procedure also results in formation of a photoresist plug in the via hole, located on an underlying, first silicon nitride stop layer. The portion of the second silicon nitride stop layer exposed in the trench shape opening is next selectively removed via a first procedure of the two step, dry etch removal procedure, followed by removal of the trench shape defining photoresist shape and of the photoresist plug. Another dry etch procedure, the second step of the two step dry etch removal procedure, is next performed to selectively remove the portion of underlying, first silicon nitride stop layer exposed in the via opening, resulting in exposure of a portion of the top surface of the conductive structure. The two step, stop layer removal procedure reduces the level of insulator corner rounding at the top of the dual damascene opening, while also reducing damage to the top surface of the underlying conductive structure, exposed at the bottom of the dual damascene opening.
REFERENCES:
patent: 6211035 (2001-04-01), Moise et al.
patent: 6211063 (2001-04-01), Liu et al.
patent: 6251774 (2001-06-01), Harada et al.
patent: 6297149 (2001-10-01), Stamper
patent: 6642153 (2003-11-01), Chang et al.
patent: 2002/0192945 (2002-12-01), Nagahara
patent: 2005/0054194 (2005-03-01), Tsai et al.
Suen Shu-Huei
Yang Fu-Kai
Gurley Lynne A.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Two step trench definition procedure for formation of a dual... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Two step trench definition procedure for formation of a dual..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two step trench definition procedure for formation of a dual... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3635905