Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-02-10
2001-12-25
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S589000
Reexamination Certificate
active
06333247
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to metal-oxide-semiconductor field effect transistor (MOSFET) designs, and more particularly, to a patterning method and design for MOSFET device gates.
2. Description of the Related Art Density, scalability, and manufacturability are important considerations in metal-oxide-semiconductor field effect transistor (MOSFET) designs. As MOSFET device miniaturization proceeds, the lithography needed to produce small device features becomes difficult. One concern is how the depth of focus of lithographic systems decreases as the size of the features to be printed decreases. This means that where small features are to be distinguished, topography on the wafers much be kept to a minimum. In miniatured devices, many elements of the device fabrication must change. Low resistance contacts to the MOSFET source and drain areas become difficult to make, and self-aligned, elevated source/drain structures look attractive for reducing source/drain series resistance and short channel effects (J. Y. Tsai and C. M. Osburn, Proc. of 6th Int. Symp. Ultralarge Scale Integration Sci. Tech., Montreal, CA, May 5-9, 1997, p. 429). Other materials that may be useful in scaled devices are high-k dielectrics like metal oxides, for example, which can raise the MOSFET gate capacitance without increasing the gate leakage current and without compromising the device breakdown characteristics.
Using metallic materials for the MOSFET gate conductors are also an important area of research, as a metal gate can reduce the gate resistance and gate delay. However, both of these materials require that processing temperature remain low, and so the materials cannot be used until after the doped source/drain areas are annealed. This problem has led to the idea of creating a dummy or stand-in MOSFET gate structure (e.g. out of nitride) instead of a real gate at the appropriate step in the process. After dummy formation, the steps of processing the source/drain regions, removing the dummy gate, depositing or growing a high-k gate dielectric, and depositing a metallic gate material are performed.
It is necessary that the new gate be self-aligned to the position and size of the dummy gate, which has led to the development of a “damascene” gate process. In the “damascene” process, the dummy gate is formed, source/drain doping is performed, a dielectric is formed and CMP is performed to planarize to the level of the topgate. Then, the dummy gate is removed, followed by forming a well, depositing the gate dielectric and gate conductor and planarizing with CMP to fill the well left behind (T. Saito, A. Yagishita, S. Inumiya, K. Nakajima, Y. Akasaka, Y. Ozawa, H. Yano, K. Hieda, K. Suguro, T. Arikado, K. Okamura, Jpn. J. Appl. Phys. 1, vol. 38, no. 4B, April 1999, p. 2227).
The result of the “damascene” gate process is an improved MOSFET device with improved and reduced device topography over a conventional MOSFET and enables the easy use of a replacement gate, but has no advantages with respect to source/drain resistance over a conventional device. In Saito's design, contacts to the source/drain must be made using an additional patterning step and cutting through the planarized oxide to reach the source/drain silicide. This means that a significant overlay tolerance must be included so that the source/drain contacts do not touch the gate.
One drawback to the Saito design is that it does not provide for a reduction in overall device size as compared to a conventional gate design. The additional patterning step and cutting require inclusion of a lithography alignment tolerance in the spacing between the source and drain contacts with respect to the gate. The lithography alignment tolerance acts as a buffer between the gate and the contact necessary to insure there not be a short between the gate and the contact when cutting the contacts. As a result of the alignment tolerance, the minimum device size is increased.
A second drawback to the Saito design is the differing source metal-to gate and drain metal-to-gate capacitances. During the additional patterning step, perfect positioning (i.e., equal distance between the gate and the metal fill on either side) is nearly impossible. As a result of the differing distances, the source/drain metal-to-gate capacitances will not be equal.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional MOSFETs the present invention has been devised, and it is an object of the present invention to provide a method for an improved MOSFET design.
This new method changes the traditional one-step MOSFET gate etch to a two-step process using two etches with a CMP planarization in-between which creates source and drain wells on two sides of the gate. Conventional, source/drain doping and silicidation may be performed inside the well. After that, the well may be filled with metal. Filling the well with metal and planarizing the gate device before backend processing reduces device topography, and reduces the demands on backend lithography while saving a masking step. These advantages will help the future scaling and miniaturization of the MOSFET device.
The present invention, in one form thereof, is a method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate. The method includes patterning and etching a mesa of gate material. At least one dielectric layer is formed or deposited on the mesa and the dielectric layer is planarized using chemical mechanical polishing (CMP). The gate material is then patterned to an active gate size and dimension and etched to form source and drain wells that extends down to the active area on either side of the gate. In one further embodiment, the method further includes filling the wells with metal and planarizing the metal.
The present invention, in another form thereof, is a method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate. The gate has a starting substrate of a semiconductor wafer having gate material of a gate dielectric, gate conductor and chemical mechanical polish stopping layers deposited thereon, and will be patterned to an active gate dimension. The method includes patterning and etching a mesa of the gate material, forming at least one dielectric layer on top of the mesa of the gate material, planarizing the at least one dielectric layer down to the chemical mechanical polishing stopping layer using chemical mechanical polishing, and then patterning and etching the remaining gate material to the active device gate dimension to form source and drain wells that extend down to active areas on either side of the MOSFET gate. In one further embodiment, the method further includes filling the wells with metal and planarizing the metal.
The present invention, in yet, another form thereof, is a method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate. The gate has chemical mechanical stopping layers deposited thereon. The method includes patterning and etching a mesa of the gate material, forming at least one dielectric layer on top of the mesa of the gate material, planarizing the at least one dielectric layer down to the polish stopping layer using chemical mechanical polishing, and patterning and etching the remaining gate material to the active device gate dimension to form source and drain wells that extend down to an active area on either side of the MOSFET gate. In one further embodiment, the method further includes filling the wells with metal and planarizing the metal.
The present invention includes a metal-oxide-semiconductor field effect transistor (MOSFET) device gate. The MOSFET gate includes a gate having layers of a dielectric and gate conductor. The gate has a first and a second side. The MOSFET gate also includes an active area on the first side and the second side. A source well is formed on the first side. A drain well is formed on the second side. Metal fill material is di
Chan Kevin K.
Jones Erin C.
Solomon Paul M.
August, Esq. Casey P.
Bowers Charles
International Business Machines - Corporation
McGinn & Gibb PLLC
Pert Evan
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