Two step memory device command buffer apparatus and method and m

Details Two step memory device command buffer apparatus and method and m Two step memory device command buffer apparatus and method and m

1997-06-13

1999-11-30

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711109, 365 78, 365 80, 36518912, 365240, G06F 1200

Patent

active

059960434

ABSTRACT:
A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of the four 10-bit command words in each packet. After the first two words of each packet have been shifted into the shift register, they are transferred to a first storage register and output from the first storage register. After the final two words of each packet have been shifted into the shift register, they are transferred to a second storage register and output from the second storage register. The first two command words are output from the first storage register before the last two command words are applied to the command buffer. As a result, the DRAM can start processing the first two command words of the command packet before the entire command packet has been received. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device.

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