Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-29
2003-04-29
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06555466
ABSTRACT:
FIELD OF INVENTION
This invention relates to the fabrication of semiconductors. More particularly, it relates to a chemical-mechanical semiconductor wafer polishing process, for use with wafers that include damascene and/or dual-damascene circuit structures, that substantially reduces “dishing” and erosion to provide improved planarity.
BACKGROUND OF INVENTION
The fabrication of very large scale integrated circuits on silicon wafers is a process requiring extreme precision because of the very fine details of the circuits. Indeed, the width of circuit lines are continually decreasing, as the technology advances, and are now in the 0.18-100 micron range. Since these circuits are produced using photolithographic techniques, extremely accurately ground lenses are required to provide such fine detail. As a necessary consequence of providing such precise focusing, the lenses lack depth of field, i.e. an image is accurately produced only at a specific distance from the lens, and any deviation in this distance produces an increasingly unfocused or fuzzy image. Therefore, the surface onto which the image is projected must be as perfectly planar as possible to eliminate out of focus image fuzziness. A failure to maintain planarity exacerbates the problem as additional layers are formed on the surface resulting in an increased proportion of defective semiconductors that must be rejected.
A standard technique for restoring surface planarity after inlaying metal in dual-damascene structures within a dielectric layer, is chemical-mechanical planarization (CMP). During this process, the surface of the wafer is polished at select intervals, with a polishing pad and a chemical slurry, to remove excess metal and to replanarize it. The slurries contain an abrasive such as silica or alumina, and chemical additives that are designed to selectively react with and soften the composition of those components that must be planarized on the wafer surface. Accordingly, polishing slurries may be selected to enhance the removal rate of a particular component on the surface of the wafer, taking into account that certain of the components may be inherently more easily removed purely by abrasive action.
While aluminum has been the preferred conductive metal used in semiconductor circuitry in the past, the more recent trend is towards the use of the damascene and dual-damascene (also known as “inlaid metallization”)process techniques that currently use copper, which is a superior electrical conductor. This trend towards using damascene and dual-damascene inlaying of metal lines and vias has presented new challenges in semiconductor fabrication. It has been found that during CMP there is often unacceptable levels of “dishing”and erosion of copper surfaces. Indeed, depressions of about 1,000Å or more may be formed. As pointed out above, as near perfect a planar surface is needed to enable modern fine line circuits. Dishing and erosion therefore present a serious issue in the new damascene and dual-damascene technology and a solution must be found.
SUMMARY OF THE INVENTION
The invention presents a chemical-mechanical planarization technique that includes a first polishing step, and a second polishing step for use with wafers that include circuits formed by damascene and dual damascene processes. The second polishing step is especially important, and includes using a slurry that has a higher removal rate for dielectric than for metal.
More particularly, in accordance with the invention, in a first step the semiconductor wafer is polished with a polishing pad and a first slurry until an end point is detected. This end point may be detected by any of a variety of techniques known in the art, which may simply be the elapse of a predetermined polishing time period. Preferably, the detection is of a type that facilitates an automatic transition to the next stage in the CMP.
Preferably, after the first polishing step, the surface of the semiconductor wafer is rinsed to remove surface debris and substantially all of the first slurry. After rinsing, polishing recommences, with a second slurry that removes the dielectric at a higher rate than the metal component. It is preferred that the rate of dielectric removal should be from about 1.2 to about 4 times greater than the rate of metal removal.
It has been found that the second polishing step reduces dishing and erosion, and repairs nonuniformities in the initial wafer surface topography left after the first polishing step. As a consequence, dishing is substantially reduced and planarization of the semiconductor wafer surface is improved, thereby facilitating the production of a higher proportion of semiconductors that meet specifications.
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Basak Sanjay
Grief Malcolm K.
Laursen Thomas
Murella Krishna P.
Hoang Quoc
Mixon Patrick L.
Nelms David
Snell & Wilmer LLP
Speedfam Corporation
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