Two-stage memory refresh circuit

Details Two-stage memory refresh circuit Two-stage memory refresh circuit

1995-12-07

1997-04-08

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Data refresh

365236, G06F 1202

Patent

active

056194684

ABSTRACT:
A timing refresh circuit refreshes a timed circuit in a functionally equivalent manner, whether the timing refresh circuit is operated at a high frequency or a low frequency. The two-stage timing refresh circuit includes a counter and combinational logic, in combination, connected between a refresh timing signal generator and a control circuit. The counter is incremented for each refresh timing signal and decremented for each refresh cycle realized by the control circuit. The combinational logic converts the counter count to a refresh signal by generating a refresh request to the control circuit whenever a count is pending in the counter.

REFERENCES:
patent: 5473770 (1995-12-01), Vrba
patent: 5475645 (1995-12-01), Wada
patent: 5511176 (1996-04-01), Tsuha

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