Two stage etching process for through the substrate contacts

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

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29580, 156644, 156651, 1566611, 357 55, 427 88, 430316, H01L 21312, B44C 122, C03C 1500, C03C 2506

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043813410

ABSTRACT:
Electrical interconnection paths or vias are provided through relatively thick type III/V semiconductive substrates, such as gallium arsenide, to permit through the substrate electrical interconnection of planar transistor devices. The vias are etched in a two-step process which ensures that the via lateral dimensions are less than the transistor contacts with which they are aligned. The first step comprises selectively thinning the thick substrate from the back surface over an area which encompasses the transistor array formed in the front surface of the substrate. The second step is to etch the individual vias through this prior thinned substrate at areas aligned with the transistor contacts.

REFERENCES:
patent: 3493820 (1970-02-01), Rosvold
IEEE Transactions on Electron Devices, vol. ED-28, No. 2, Feb. 1981, Monolithic Microwave Amplifiers Formed by Ion Implantation into LEC, Gallium Arsenide Substrates by M. C. Driver et al., pp. 191-196.

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