Two-stage Cu anneal to improve Cu damascene process

Details Two-stage Cu anneal to improve Cu damascene process Two-stage Cu anneal to improve Cu damascene process

2001-05-02

2002-05-21

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S678000

Reexamination Certificate

active

06391777

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of integrated circuits in general, and in particular, to a two stage copper anneal process to suppress hillock formation in Cu dual damascene process used in manufacturing semiconductor products.
(2) Description of the Related Art
Copper is preferred in forming metal interconnects in ultra-large scale integrated (ULSI) semiconductor devices. This is because, as semiconductor device geometries continue to scale down below 0.25 &mgr;m, and approach 0.13 &mgr;m feature sizes, the metal interconnect lines which carry current between devices on a chip begin to dominate the overall circuit speed. In order to enhance interconnect speed and reliability, the semiconductor industry is moving away from blanket deposition and etch of aluminum (Al) based metallization towards single-damascene and dual-damascene interconnect structures with copper (Cu) based metallizations. Copper is a lower resistivity metal than aluminum, which results in lower RC interconnect delay. Copper has also been shown to have superior electromigration characteristics over aluminum, but is more difficult to process, primarily because it is more difficult to etch, and it acts as deep level trap in silicon (Si) based devices. The preferred way to process copper interconnects is to etch a line trench, via hole, or a contact hole into a dielectric material, deposit the interconnect metallization to fill the trench or hole, and then polish the metal back to remove any metal from the surface of the substrate or wafer. The resulting metal-filled trenches and holes form the electrical interconnect. Forming an interconnect structure by filling a trench or hole with metal is known as a damascene process. If a trench an underlying via hole are filled simultaneously, it is known as a dual-damascene process.
The process of forming conventional single or dual-damascene structures is shown in
FIGS. 1
a
-
1
c
. In one approach, two insulator layers (
120
) and (
130
) are formed on a substrate (
100
) with an intervening etch-stop layer (
125
), as shown in
FIG. 1
a
. Substrate (
100
) is provided with metal layer (
110
) and a barrier layer (
115
). Using conventional photolithographic methods and photoresist (
160
), the upper insulator layer (
130
) is first etched, or patterned, with hole (
170
), as shown in
FIG. 1
a
. The hole pattern is also formed into etch-stop layer (
125
). Then, the first photoresist mask is replaced with second mask (
140
) having a trench pattern, and the upper layer is etched to form trench (
150
) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (
120
), as shown in
FIG. 1
b
. It will be noted that the etch-stop layer stops the etching of the trench into the lower insulation layer. After the completion of the thusly formed dual damascene structure, both the hole opening and trench opening are filled with metal (
180
), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in
FIG. 1
c.
Or, the order in which the trench and the hole are formed can be reversed (not shown) . That is, using a first photoresist mask, a desired trench or trench pattern is first etched into the upper insulator material (
130
). The etching stops on etch-stop layer (
125
). Next, a second photoresist layer is formed over the substrate, thus filling the trench opening (
150
), and patterned with hole opening (
170
). The hole pattern is then etched into the lower insulator layer (
120
) and photoresist removed, thus forming the dual damascene structure shown in
FIG. 1
c
. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers.
As desirable as the functional properties of copper are for forming interconnects, reliability of copper interconnects can be further improved. Nogami, et al., in U.S. Pat. No. 6,103,624 propose to increase the electromigration reliability to theoretically calculated levels. To accomplish this, a barrier metal layer is applied over the surface of a dielectric layer with a plurality of trenches. The barrier metal layer lines the trenches. A copper layer is placed over the barrier metal layer and fills the trenches. The part of the copper layer that is not inside the trenches is polished away. The copper layer is laser annealed to increase the grain size of copper, and provide a better interface bond between the barrier metal layer and the copper layer. The barrier metal layer protects the dielectric layer during the annealing process. That part of the barrier metal that is not in the trenches is removed by polishing. The larger grain size improves electromigration reliability of the device.
Another improvement to electromigration resistance is disclosed by Andricacos, et al., in U.S. Pat. No. 6,090,710 for copper alloys containing 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin. The copper alloy is annealed to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy.
In addition to the electromigration problem addressed by prior art, the present invention addresses another reliability problem with copper interconnects, namely, hillock formation due to stresses built in copper as a result of the various process steps in forming semiconductor devices. The method involves a two-stage annealing process which is disclosed in the embodiments of the present invention.
Hillocks are spike-like projections that erupt in response to a state of compressive stress in metal films and consequently protrude from the film's surface, as shown in
FIG. 1
d
. Thus, after a dual damascene interconnect such as (
180
) in
FIG. 1
c
has been formed, another intermetal dielectric (IMD) layer (
190
) is formed over the substrate. However, because of almost ten times the difference in the thermal coefficient of expansion between dielectrics and metals −1.7×10
−6
/° C. versus 17×10
−6
/° C., respectively- metals, such as copper on a substrate, want to expand more than allowed by the substrate and dielectric expansion, but cannot, assuming the adhesion between the layers is adequate. As a result, compressive stresses build in the metal film. If they become too large (i.e., the process temperature exceeds ~300° C.), the stresses are relieved by the growth of hillocks at the film surface, as referenced by numeral (
200
) in
FIGS. 1
e
and
1
f
. The judicious two-stage annealing of the copper that is disclosed in the present invention relieves the stresses and, therefore, prevents hillock formation, as described more in detail below in the embodiments of the invention.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method to suppress or avoid hillock formation in forming copper dual damascene structures.
It is another object of the present invention to provide a method of performing a two-stage copper annealing in order to prevent hillock formation.
It is an overall object of the present invention to provide a method of improving the reliability of copper dual damascene interconnects by suppressing the formation of hillocks.
These objects are accomplished by providing semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon; forming an insulative dielectric layer over said substrate; forming a damascene structure within said insulative dielectric layer; forming a barrier layer in said damascene structure; forming a seed layer over said barrier layer; forming ECP copper over said seed layer in said damascene structure using electro-chemical plating (ECP); performing a first anneal of said copper; removing any exc

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