Two-stage clock tree synthesis with buffer distribution...

Details Two-stage clock tree synthesis with buffer distribution... Two-stage clock tree synthesis with buffer distribution...

2006-05-23

2006-05-23

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07051310

ABSTRACT:
A clock tree synthesis (CTS) tool determines how to position a hierarchy of buffers for fanning out a clock signal to clocked devices (“sinks”) within an integrated circuit (IC). The tool first clusterizes the sinks and places a lowest level fan-out buffer near each cluster. The tool then iteratively places progressively higher level buffers by clusterizing a last-placed buffer level and then placing a next higher level buffer near the centroid of each lower level buffer cluster, until the tool has placed buffers at a mid-level for which variation in path distances between that level and a next higher buffer level exceeds a predetermined limit. The CTS tool then places a top level buffer at the centroid of the mid-level buffers, divides the layout into partitions, each containing a similar number of mid-level buffers, and then places a second-highest level buffer in each partition. The CTS iteratively places each next lower buffer level by dividing each partition into progressively smaller partitions and placing progressively lower level buffers in each smaller partition until it places buffers at a level having sufficient number of buffers to drive the mid-level buffers.

REFERENCES:
patent: 6367060 (2002-04-01), Cheng et al.
patent: 6609228 (2003-08-01), Bergeron et al.
patent: 2003/0134836 (2003-07-01), Chang et al.
Mehta et al., Clustering and Load Balancing for Buffered Clock Tree Synthesis, Proceedings of the 1997 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 12, 1997, pp. 217-223.

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