Two-port two-transistor DRAM

Details Two-port two-transistor DRAM Two-port two-transistor DRAM

1989-11-09

1991-04-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365149, 365222, 36523005, G11C 1140, G11C 1300

Patent

active

050070223

ABSTRACT:
A DRAM array having a number of two-port cells (10) arranged to permit the simultaneous read and write operations of different cells within the array. Each column of the array includes a refresh circuit (40) which is responsive to a four-phase clock for carrying out refresh operations which are transparent to the programmer. When used in microcomputer applications having four-phase clocks, the DRAM array of the invention functions similar to a static RAM, in that refresh is automatically undertaken.

REFERENCES:
patent: 4447891 (1984-05-01), Kadota
patent: 4506322 (1985-03-01), Leigh
patent: 4546273 (1985-10-01), Osman
patent: 4677592 (1987-06-01), Sakurai et al.
patent: 4679172 (1987-07-01), Kirsch et al.
patent: 4716548 (1987-12-01), Mochizuki
patent: 4739502 (1988-04-01), Nozaki
patent: 4740926 (1988-04-01), Takemae et al.
patent: 4760559 (1988-07-01), Hidaka et al.
patent: 4780849 (1988-10-01), Nakagawa et al.
patent: 4794571 (1988-12-01), Uchida

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