Two-port SRAM having improved write operation

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S226000, C365S156000

Reexamination Certificate

active

07440313

ABSTRACT:
A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

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Tran; “Demonstration of 5T SRAM and 6T Dual-Port RAM Cell Arrays” 1996 Symposium on VLSI Circuits Digest of technical Papers, IEEE.
International Search Report for coordinating PCT Application No. PCT/US07/79709 mailed May 28, 2008.

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