Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-08-18
2001-07-17
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S001000
Reexamination Certificate
active
06263390
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to microprocessors and, more particularly, to an IO (Input Output) gateway subsystem of a microprocessor that includes a two-port memory to connect a microprocessor bus to multiple peripherals.
BACKGROUND OF THE INVENTION
A microprocessor typically includes an IO (Input Output) gateway subsystem for connecting multiple peripherals to a microprocessor bus. A system memory and controller is also typically connected to the microprocessor bus. Specifically, the IO gateway subsystem acts as a gateway between multiple IO devices and the microprocessor bus. The IO gateway allows the multiple IO devices to transfer data to and from the system memory via the microprocessor bus.
More specifically, the IO gateway subsystem of a microprocessor typically includes various interfaces that manage read and write requests between the multiple IO devices and the microprocessor bus. An interface such as a DMA (Direct Memory Access) interface typically includes a DMA engine that queues the read and write requests of multiple DMA devices in a shared DMA buffer. The DMA engine typically arbitrates access to the shared DMA buffer among the multiple IO devices.
SUMMARY OF THE INVENTION
The present invention provides a two-port memory to connect a microprocessor bus to multiple peripherals. For example, the present invention provides a cost-effective and high performance apparatus and method for an IO gateway subsystem of a microprocessor (e.g., a system) that includes a two-port memory to connect a microprocessor bus to multiple peripherals.
In one embodiment, an apparatus for an IO gateway subsystem of a microprocessor includes a first interface and a second interface (e.g., a DMA interface and a PCI interface, which can each be connected to multiple IO devices). A two-port memory of the IO gateway subsystem is connected to a global bus of the microprocessor. The two-port memory is also connected to the first interface and to the second interface. In particular, the first interface and the second interface arbitrate to access the microprocessor bus via the connection between the two-port memory and the microprocessor bus. The first interface is connected to a first buffer of the two-port memory via a first interface connection. Also, the second interface is connected to a second buffer of the two-port memory via a second interface connection. Accordingly, the first interface is not required to arbitrate with the second interface to access the first buffer of the two-port memory, and the second interface is not required to arbitrate with the first interface to access the second buffer of the two-port memory.
In one embodiment, an apparatus for an IO gateway subsystem of a microprocessor includes a two-port memory. The two-port memory of the IO gateway subsystem is connected to a global bus of the microprocessor. In particular, the connection between the two-port memory and the global bus of the microprocessor is synchronized with a global clock (e.g., a CPU (Central Processing Unit) clock that is characterized by a frequency and a phase). The two-port memory of the first interface includes a first buffer for a first IO device and a second buffer for a second IO device. The first buffer is connected to the first IO device via a first IO device connection. Also, the second buffer is connected to the second IO device via a second IO device connection. In particular, the first IO device connection is synchronized with a first IO device clock, and the second IO device connection is synchronized with a second IO device clock. The first IO device clock rate and the second IO device clock rate can be different (asynchronous), and further, the first IO device clock rate, the second IO device clock rate, and the global clock rate can all be different. Moreover, the first IO device is not required to arbitrate with the second IO device to access the first buffer of the two-port memory, and similarly, the second IO device is not required to arbitrate with the first IO device to access the second buffer of the two-port memory.
In one embodiment, the IO gateway subsystem includes a PCI (Personal Computer Interface), a display interface, and a DMA interface. Each of the interfaces is connected to its own buffer of a two-port memory. Thus, the interfaces do not arbitrate with each other to access their own buffer of the two-port memory. The two-port memory is also connected to a global bus of the microprocessor. The DMA interface is connected to multiple IO devices (e.g., eight IO devices). The two-port memory connected to the DMA interface includes a buffer for each IO device. Each IO device has its own connection to its buffer. Thus, the IO devices do not arbitrate with each other to access the two-port memory. Further, each IO device operates on its own clock, and the synchronization between the DMA buffers and the IO devices is handled by the DMA interface. Alternatively, synchronization is not required (e.g., the clock rates can have identical frequencies but asynchronous phases, or also have asynchronous frequencies) if the IO devices operate on a divided synchronous clock with respect to the DMA interface clock.
In one embodiment, a method includes communicating via a first port of a bank (e.g., a cache line or multiple cache lines) of a two-port memory at a first clock rate (e.g., frequency and phase) with a first peripheral, and communicating via a second port of the bank of the two-port memory with a bus of a microprocessor at a second clock rate (e.g., frequency and phase), in which the first and second clocks can have different (asynchronous) frequencies, or the first and second clocks can have different phases (when the frequencies are identical).
Other aspects and advantages of the present invention will be come apparent from the following detailed description and the accompanying drawings.
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Alasti Ali
Malalur Govind V.
ATI International SRL
Kwok, Esq. Edward C.
Myers Paul R.
Skjerven Morrill & MacPherson LLP
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