Error detection/correction and fault detection/recovery – Pulse or data error handling – Error detection for synchronization control
Reexamination Certificate
2005-09-28
2011-12-13
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error detection for synchronization control
Reexamination Certificate
active
08078948
ABSTRACT:
A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.
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patent: 6999542 (2006-02-01), Korger et al.
Jacobs et al: “A Fully Asynchronous Digital Signal Processor Using Self-Timed Circuits”; IEEE Journal of Solid-State Circuits; vol. 25 No. 6; Dec. 1990; pp. 1526-1537.
Furber et al: “Amulet3: A 100 MIPS Asynchronous Embedded Processor”; IEEE Computer Design 2000 International Conf.; Sep. 17-20, 2000; pp. 329-334.
Pontius Timothy
Roever Jens
Chase Shelly A
NXP B.V.
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