Two-phase clock-stalling technique for error detection and...

Details Two-phase clock-stalling technique for error detection and... Two-phase clock-stalling technique for error detection and...

2008-10-22

2011-10-18

Spittle, Matthew (Department: 2111)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S002000, C714S048000, C714S049000, C714S731000, C714S744000, C713S400000, C713S401000, C713S600000, C713S601000

Reexamination Certificate

active

08042010

ABSTRACT:
One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block.

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