Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond
Reexamination Certificate
2002-09-10
2004-04-06
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Solder wettable contact, lead, or bond
C257S678000
Reexamination Certificate
active
06717276
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally related to the field of semiconductor assembly and packaging, and more particularly, to the field of packaged semiconductor devices in a flip chip format or wire-bonded format.
BACKGROUND OF THE INVENTION
Many semiconductor devices are typically packaged on a single layer substrate of medium or low electrical performance characteristics. Generally, the costs of packaging a semiconductor chip on a multi-layer, high performance substrate can be high depending on the design format of the device as well as on the number of devices that are produced. Semiconductor manufacturers have attempted to lower the cost of multi-layer substrate packaged devices by standardizing design rules and manufacturing techniques, but have not yet achieved customer cost expectations. One of the primary reasons for the increased cost of the multilayer substrate design is the processing required to electrically connect the various metal layers in the substrate. Presently this is done by the substrate suppliers themselves and then provided to the assembly operations. The conventional methods of providing electrical interconnections between the different associated layers of the multi-layer substrate are electrolessly deposited and/or sputtered metals providing the interconnect between the multiple layers. These two process techniques are generally expensive and time-consuming.
Thus, there is desired a technique in semiconductor chip assembly and packaging of cost-effectively providing a local electrical interconnect between two or more metal substrate layers without having to use the conventional methods. Such a technique would greatly improve the performance of a semiconductor chip packaged in either a flip-chip or a wire-bonded format while not reducing electrical performance. Moreover, such a technique would greatly shorten the time in which a semiconductor chip is packaged and, in turn, will lower its production costs.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a low cost apparatus and method of providing a layer-to-layer electrical interconnect between two metal layers used in the assembly of flip-chip and wire-bonded packages. Advantageously, the present invention provides for an electrical connection between the two metal layers to he made without using conventional methods of forming the interconnect, such as, by electrolessly depositing the interconnect, for example. The invention also advantageously allows for a layer-to-layer connection to be achieved between the two metal layers without using a sputtered interconnect.
In one embodiment, the present invention is a two metal layered ball grid array having generally planar first and second metal layers. The second metal layer includes a plurality of openings at spaced intervals across the surface thereof. The invention also includes an organic tape layer coupled between the first and second metal layers. In a selected embodiment, the organic tape layer is preferably comprised of a dielectric material, such as a copper-coated polyimide tape. The organic tape layer also has a plurality of vias at spaced intervals and which are aligned with the openings of the second metal layer. Preferably, these vias function as receiving channels for receiving a conductive material, such as solder paste, for example. Further, the invention includes a plurality of solder balls aligned with the openings of the second metal layer such that the solder balls are adapted to attach to the solder paste to form a series of electrical interconnects. The solder balls run substantially in parallel between the first and second metal layers.
In another embodiment, a method of forming one or more interconnects between the first and second metal layers is presented. The method includes forming a plurality of vias spaced apart along an organic tape layer such that the vias provide an interconnect between the two metal layers. The method of the present invention also includes the step of forming a plurality of corresponding openings across the surface of one of the metal layers and generally near the vias of the organic tape layer. Solder paste is deposited in the respective vias and a plurality of solder balls are attached across the respective openings of the second metal layer such that the solder balls are heat wetted to the solder paste to form a plurality of substantially parallel electrical interconnects between the first and second metal layers.
REFERENCES:
patent: 5866942 (1999-02-01), Suzuki et al.
patent: 6350668 (2002-02-01), Chakravorty
patent: 6477046 (2002-11-01), Stearns et al.
patent: 6486549 (2002-11-01), Chiang
Murtuza Masood
Walter David N.
Brady III Wade James
Nhu David
Tung Yingsheng
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