Two-layered gate structure for a semiconductor device and method

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation

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438225, 257316, 257324, 257326, 257508, H01L 2978, H01L 2110

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active

060543663

ABSTRACT:
In order to avoid any concentration of an electric field to gate edges of a two-layered structure and to improve an accumulation performance of charge, a semiconductor device includes a semiconductor substrate; an element isolation region formed to define an element formation region in the semiconductor substrate; a first gate insulating layer formed in a part of a surface of the element formation region; a first gate electrode formed on the first gate insulating layer; an insulating layer for surrounding the first gate electrode with a top surface of the insulating layer being substantially in the same plane as that of a top surface of the first electrode; a second gate insulating layer formed on the first gate electrode; and a second gate electrode formed on the second gate insulating layer. Also, a method therefor is provided.

REFERENCES:
patent: 4539744 (1985-09-01), Burton
patent: 5036375 (1991-07-01), Mitchell
patent: 5312770 (1994-05-01), Pasch
patent: 5472892 (1995-12-01), Gwen et al.
patent: 5882985 (1995-10-01), Wang et al.

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