Two-layered gate structure for a semiconductor device and method

Details Two-layered gate structure for a semiconductor device and method Two-layered gate structure for a semiconductor device and method

1997-06-10

1998-09-15

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257324, 257326, 257508, H01L 2972

Patent

active

058083391

ABSTRACT:
In order to avoid any concentration of an electric field to gate edges of a two-layered structure and to improve an accumulation performance of charge, a semiconductor device includes a semiconductor substrate; an element isolation region formed to define an element formation region in the semiconductor substrate; a first gate insulating layer formed in a part of a surface of the element formation region; a first gate electrode formed on the first gate insulating layer; an insulating layer for surrounding the first gate electrode with a top surface of the insulating layer being substantially in the same plane as that of a top surface of the first electrode; a second gate insulating layer formed on the first gate electrode; and a second gate electrode formed on the second gate insulating layer. Also, a method therefor is provided.

REFERENCES:
patent: 5036375 (1991-07-01), Mitchell
patent: 5472892 (1995-12-01), Gwen et al.

Affiliated with

Also associated with

Rating

Two-layered gate structure for a semiconductor device and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two-layered gate structure for a semiconductor device and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two-layered gate structure for a semiconductor device and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-91294