Two-gate non-coplanar FET with self-aligned source

Details Two-gate non-coplanar FET with self-aligned source Two-gate non-coplanar FET with self-aligned source

1983-12-09

1985-08-27

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29571, 29580, 148187, 156653, 156657, 1566591, 156662, 357 41, 427 88, H01L 21306, B44C 122, C03C 1500, C23F 102

Patent

active

045376549

ABSTRACT:
A two-gate non-coplanar field-effect transistor and a method for its fabrication. An active semiconductor layer is formed over a stop-etch layer on a substrate of semi-insulating material, such as gallium arsenide, and a via hole is formed from the opposite face of the substrate, through to the stop-etch layer. The via hole is metallized and located from the active-layer side of the device using an electron-beam technique. A two-element gate structure is then formed over the active layer, in approximate alignment with the via hole. Then a source region is ion-implanted into the active layer and into the stop-etch layer, using the positions of the gate elements to self-align the source. Drain contact regions are also formed in the active layer by ion implantation. Contact between the source region and the metallized via hole does not depend on accurate and uniform etching of the via hole. Instead, an opening is etched through the source region to the via hole, and filled with ohmic metal to make good contact with the via hole metallization.

REFERENCES:
patent: 4141021 (1979-02-01), Decker
patent: 4142926 (1979-03-01), Morgan
patent: 4180422 (1979-12-01), Rosvold

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