Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2000-03-20
2001-09-04
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S071000, C365S072000, C365S168000
Reexamination Certificate
active
06285582
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates a static memory architecture, in particular to a resonant tunneling diode multiple-valued memory system. This is a co-pending patent application of U.S. patent application Ser. No. 09/512,049.
(2) Description of the Related Art
In U.S. Pat. No. 5,280,445, a multiple-dimensional RTD memory cell was disclosed, where a single RTD memory cell can store a large number of states, as compared to a conventional binary memory cell, which can only store two states, namely: the “0” logic state and the “1” logic state.
An RTD has a folding voltage-current (V-I) characteristic as shown in
FIG. 1
, curve (a) where the positive slope of the V-I characteristic represents positive differential resistance and the negative slope of the V-I characteristic represents negative differential resistance. When the positive resistance is connected in series with the RTD, the positive differential resistance is increased and the negative differential resistance is reduced as shown in
FIG. 1
, curve (b). Further increase in the series resistance causes the V-I characteristic to yield a folding characteristic with hysteresis as shown in FIG.
2
.
The multiple-dimensional RTD memory cell disclosed in U.S. Pat. No. 5,280,445 utilizes this hysteretic characteristic. When two RTDs RTDu and RTDd each with a one-peak hysteretic folding V-I characteristic are connected in series through a resistance R as shown in
FIG. 3
, the circuit becomes a 4-state memory cell. The cell can have four stable states as depicted in FIG.
4
. The stable operating points are the intersections S
1
, S
2
, S
3
, S
4
of the positive differential resistance sections of the folding characteristics. By applying two different voltages V
H
and V
L
across the resistance, the memory cell can be set (written) to the different memory states. In this figure, Vpu, Vvu, and Vpd. Vvd denote the peak and valley of RTDu and RTDd, respectively. During writing, when V
L
is less than Vp
1
, the positive differential resistance ra
1
is effective, and when V
L
exceeds Vpd, rd
2
is effective. Similarly, when V
H
is higher than Vpu, ru
1
is effective, and when V
H
is less than Vpu, rub
2
is effective. The stable operating points are determined by the intersections of the effective differential resistances. Thus, by applying different combinations of V
L
and V
H
, the memory cell can be set to different memory states.
In a copending U.S. patent application, Ser. No. 09/512,049, it was disclosed that a 2-dimensional RTD memory cell can also be accessed by sensing its node voltage Vm and its series current Im, as shown in FIG.
5
.
While the RTD memory cell was disclosed in the U.S. Pat. No. 5,380,445 and in the copending application Ser. No. 09/512,049, the architecture for incorporating the RTD memory cell was not disclosed.
SUMMARY OF THE INVENTION
An object of this invention is to disclose an architecture for incorporating RTD memory cells in a static memory system, in particular to a two-dimensional RTD memory. Another object of this invention is to design an RTD memory system to minimize the number of peripheral circuits and devices. Still another object of this invention is to design an RTD memory system wherein the memory cell is accessed by sensing two node voltages, or by sensing a node voltage and a series current during reading. A further object of this invention is to provide binary data input and store in the RTD memory cell as multiple-valued digital data.
These objects are achieved by placing the RTD memory cells at the cross-points of a memory matrix. Each memory cell has two inputs corresponding either to two node voltages V
H
and V
L
in
FIG. 3
or two sequential node voltages: the pull-up voltage Vu and the pull-down voltage Vd in FIG.
5
. The outputs of each cell are the node voltage Vm and Vi which is proportional to the series current Im.
For a multi-valued data input, the data can first be converted by an analog-to-digital converter (ADC) into binary data, which are split into two binary words. One binary word is reconverted by a digital-to-analog converter (DAC) into a first multi-valued data to serve as V
H
or Vu and the other binary word is reconverted into a second multi-valued data to serve as V
L
or Vd. The multiple-valued data are arranged as a two-dimensional X-Y matrix. Each X-value and a Y-value correspond to a unique memory state of the multiple-valued memory state.
The multi-valued data stored in the memory cell can be read by sensing the node voltage Vm and the series current Im. The multi-valued node voltage is converted as the one section (say MSB) of a binary word, and the multi-valued series current is converted as another section (say LSB) of the binary word. The two sections of the binary word are combined in an output DAC and converted into a multi-valued output.
For binary data input, the input ADC at the input can be eliminated. For binary output, the output DAC can be eliminated.
REFERENCES:
patent: 5280445 (1994-01-01), Shieh et al.
patent: 5572626 (1996-11-01), Lin et al.
patent: 5654921 (1997-08-01), Sano
patent: 5714891 (1998-02-01), Lin et al.
patent: 5953249 (1994-01-01), Van Der Wagt
Epitaxial Technologies LLC
Le Vu A.
Nguyen Vanthu
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