Two-dimensional resonant tunneling diode memory cell

Details Two-dimensional resonant tunneling diode memory cell Two-dimensional resonant tunneling diode memory cell

2001-10-10

2002-11-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S105000

Reexamination Certificate

active

06480413

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to semiconductor memory—in particular to memory cell using resonant tunneling diodes.(RTD)
(2) Brief Description of the Related Art
In U. S. Pat. No. 5,280,445, a multiple-dimensional RTD memory cell was disclosed, where a single RTD memory cell can store a large number of states, as compared to a conventional binary memory cell, which can only store two states, namely: the “0” logic state and the “1” logic state.
An RTD has a folding voltage-current (V-I) characteristic as shown in
FIG. 1
, curve (a), where the positive slope of the V-I characteristic represents positive differential resistance and the negative slope of the V-I characteristic represents negative differential resistance. When the positive resistance is connected in series with the RTD, the positive differential resistance is increased and the negative differential resistance is reduced as shown in
FIG. 1
, curve (b). Further increase in the series resistance causes the V-I characteristic to yield a folding characteristic with hysteresis as shown in FIG.
2
.
The multiple-dimensional RTD memory cell disclosed in U.S. Pat. No. 5,280,445 utilizes this hysteretic characteristic. When two RTDs, RTDu and RTDd each with a one-peak hysteretic folding V-I characteristic are connected in series through a resistance R as shown in
FIG. 3
, the circuit becomes a
4
-state memory cell. The cell can have four stable states as depicted in FIG.
4
. The stable operating points are the intersections S
1
, S
2
, S
3
, S
4
of the positive differential resistance sections of the folding characteristics. By applying two different voltages V
H
and V
L
across the resistance, the memory cell can be set (written) to the different memory states. In this figure, Vpu,Vvu, and Vpd. Vvd denote voltages at the peak current and valley current of RTDu and RTDd, respectively. During writing, when V
L
is less than Vp
1
, the positive differential resistance ra
1
is effective, and when V
L
exceeds Vpd, rd
2
is effective. Similarly, when V
H
is higher than Vpu, ru
1
is effective, and when V
H
is less than Vpu, rub
2
is effective. The stable operating points are determined by the intersections of the effective differential resistances. Thus, by applying different combinations of V
L
and V
H
, the memory cell can be set to different memory states.
The memory cell shown in
FIG. 3
as well as that in U.S. Pat. No. 5,280,445 requires a resistor R. The resistor R occupies area in the layout of a memory. In a memory integrated circuit, it is desirable to minimize the memory cell area to increase packing density,
SUMMARY OF THE INVENTION
An object of this invention is to eliminate the resistor in the memory cell in the prior art. Another object of this invention is to sense both the node voltage and the series current of a two dimensional RTD memory cell. Still another object of this invention is to minimize the area of the memory.
These objects are achieved by eliminating the resistor in the memory cell and use only one terminal to access the memory cell. The memory state is determined by the node voltage and the series current of two RTDs with hysteretic V-I characteristics connected in series. During writing, two pulses are applied to the node. One of the pulses selects the effective positive differential resistance characteristic of the pull-down RTD. Another pulse selects the effective positive resistance characteristic of the pull-up RTD. The intersecting point of the two characteristics determines the memory state.
During reading, the node voltage and the series current is sensed. A current sensor is connected in series with the ground terminal of the power supply for the memory cell. The sensor is short-circuited during writing. During reading, the current sensor presents a virtual ground. The current sensor is shared by a large number of memory cells and is connected in series with a bank of memory cells. During reading, only one of the memory cells is connected to the current sensor to sense the current through that particular memory cell.


REFERENCES:
patent: 5267193 (1993-11-01), Lin
patent: 5280445 (1994-01-01), Shied et al.
patent: 5390145 (1995-02-01), Nakasha et al.
patent: 5883829 (1999-03-01), Van der Wagt
patent: 5953249 (1999-09-01), Van der Wagt

Affiliated with

Also associated with

Rating

Two-dimensional resonant tunneling diode memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two-dimensional resonant tunneling diode memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two-dimensional resonant tunneling diode memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2987464