Two dimensional data eye centering for source synchronous...

Details Two dimensional data eye centering for source synchronous... Two dimensional data eye centering for source synchronous...

2006-04-25

2006-04-25

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data pulse evaluation/bit decision

C714S719000, C714S721000, C714S744000

Reexamination Certificate

active

07036053

ABSTRACT:
A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

REFERENCES:
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patent: 2003/0226070 (2003-12-01), Fukao et al.

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