Two-dimensional C-element array

Details Two-dimensional C-element array Two-dimensional C-element array

2002-06-28

2003-11-25

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C326S038000, C326S039000, C716S030000

Reexamination Certificate

active

06654944

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to providing improved clocking in synchronous high-speed semiconductor chips. More particularly, the present invention relates to using the unique properties of a two-dimensional C-element array to provide, among other advantages, source synchronous transfer of data, localized clock sources with frequencies responsive to voltage, temperature, and usage, and reduced power consumption in the chips.
2. Description of the Related Art
Semiconductor devices, also referred to herein as “chips,” may comprise digital circuits having components that typically operate in synchronism. “Synchronism” means that, in such devices, clocks may be utilized to synchronize events among digital components such as flip-flops, multiplexers, adders, and multipliers. A clock may generate a series of sequential square wave pulse signals that transition from a low state (i.e., logic “0”) to a high state (i.e., logic “1”) and back again in a periodic manner. The series of pulses, also known as a pulse train, may be sent by the clock through conductive lines to each of the digital components to indicate when specific operations must be performed.
Digital circuits are typically triggered by the “active” edge of a clock cycle. The active edge is typically the rising edge of the square wave pulse, although it may sometimes be on the falling edge of the pulse. A digital circuit usually requires its clocked components to be synchronized with active edges of the clock cycles to function properly.
In a typical design today, the clock is generated independently of the data and does not travel in conjunction with data to the data receiver. By contrast, “source synchronous” clocking means that a source device sends clocking information, along with data, to a receiving device.
In a conventional semiconductor chip, the clock is typically driven by a phased-locked loop (PLL), which is a commonly used circuit in modern electronics systems. PLL circuits oscillate to match in phase and lock onto the frequency of an input signal. A PLL circuit may be used for many purposes, such as generating, modulating or demodulating a signal or removing noise from a signal. PLL circuits are also used to recover a clock signal based on an input reference signal.
A conventional PLL circuit includes a voltage-controlled oscillator (VCO) and a phase detector in a feedback loop. The VCO generates an output frequency, which is input to the phase detector. The phase detector then causes the VCO to seek and lock onto the desired frequency, based on the difference between the output of the VCO and the input signal. If a difference exists, the phase detector generates an error voltage that is used to bring the VCO to the correct frequency.
Although PLL circuits have become the standard with which circuits are coordinated with clock pulses, PLL circuits have certain characteristics that limit their effectiveness in clocking applications. For example, analog adjustments in PLL-driven clocking frequency in response to changing circuit conditions such as voltage, temperature and usage are difficult to achieve. Such adjustments are difficult to make, for example, because typically a PLL is only able to detect clocking phase problems at certain checkpoints throughout the chip and respond through a feedback system. Furthermore, the inability of PLL-driven clock circuits to readily make adjustments in frequency based on changing circuit conditions means that often power is wasted. Since, for example, a low frequency task requires less power than a high frequency task, a PLL-driven clock circuit by design is unable to conserve power when a processor is executing a low frequency task, because usually the clock circuit runs at a fixed, higher frequency.
PLL circuits also have certain limitations that will render them unable to service future generations of chips with much higher clock speeds. Following Moore's Law, which has held true since 1965, the number of transistors on an integrated circuit will double every 18 months. Therefore, by mid-2003, processors may be running at four to five gigahertz. In 2005, it may be possible to attain speeds up to ten gigahertz. As clock speeds increase, chips having clocks driven by PLL circuits will be unable to adjust their frequency to temperature, voltage, and usage variations in an efficient manner.
In view of the above discussion, a system is called for that overcomes the limitations and problems of PLL circuits as described above.


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