Two-dimensional array transposition circuit reading two-dimensio

Details Two-dimensional array transposition circuit reading two-dimensio Two-dimensional array transposition circuit reading two-dimensio

1998-01-21

2000-08-15

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

708402, G06F 1200

Patent

active

061051144

ABSTRACT:
A two-dimensional array transposition circuit having a small circuit scale and accordingly having a small power consumption includes a memory cell array capable of storing a two-dimensional array and an address translation circuit receiving an address signal and generating a row address signal and a column address signal for specifying a memory cell of the memory cell array via a row decoder and a column decoder. The address translation circuit generates, when one two-dimensional array is written into the memory cell array, a row address signal and a column address signal successively such that an order of writing is according to one of an order giving priority to a row direction and selecting a memory cell and an order giving priority to a column direction and selecting a memory cell and generates, when the two-dimensional array is read from the memory cell array, a row address signal and a column address signal successively such that an order of reading is according to the other order.

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"A 100 MHz 2-D Discrete Cosine Transform Core Processor", Uramoto et al., IEEE Journal Of Solid State Circuits, vol. 27, No. 4, Apr., 1992.

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