Two-device memory cell on SOI for merged logic and memory applic

Details Two-device memory cell on SOI for merged logic and memory applic Two-device memory cell on SOI for merged logic and memory applic

1997-06-13

1998-07-21

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

365182, 365181, 36523005, G11C 1124

Patent

active

057843112

ABSTRACT:
A two-MOSFET device memory cell, based on conventional SOI complementary metal oxide technology, in which charge is stored on the body of a first MOSFET, with a second MOSFET connected to the body for controlling the charge in accordance with an information bit. Depending on the stored charge, the body of the first MOSFET is in depletion or non-depletion condition. A reference voltage connected to the gate of the first MOSFET causes a bipolar current flow in response to a pulsed voltage on the first MOSFET's source when the MOSFET is in a non-depletion condition, due to a temporary forward bias of the source to body junction. The bipolar current substantially adds to the field-effect current, thereby multiplying the effective charge read from the first MOSFET.

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