Two-cycle return path clocking

Details Two-cycle return path clocking Two-cycle return path clocking

2011-02-15

2011-02-15

Zaman, Faisal M (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S060000, C713S501000, C713S503000

Reexamination Certificate

active

07890684

ABSTRACT:
Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device may transmit data to one or more of the slave devices at a rate of one bit per clock cycle. One or more of the slave devices may transmit data to the master device at a rate of one bit per two consecutive clock cycles. The master device may sample the transmitted data on the second cycle of each two consecutive clock cycle period. Alternatively, the slave devices may transmit data to the master device at a rate of one bit per N consecutive clock cycles, where N≧2, and the master device may sample the transmitted data on the Nthcycle of each N consecutive clock cycle period.

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