Static information storage and retrieval – Read/write circuit – Serial read/write
Patent
1994-12-19
1996-08-27
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Serial read/write
365 73, 365 78, 36518705, 365239, G11C 700
Patent
active
055507808
ABSTRACT:
A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.
REFERENCES:
patent: 3166715 (1965-01-01), Cogar
patent: 3212009 (1965-10-01), Parker
patent: 3300724 (1967-01-01), Cutaia
patent: 3378776 (1968-04-01), Goldberg et al.
patent: 3460098 (1969-08-01), De Blauw
patent: 3510680 (1970-05-01), Cogar
patent: 3727204 (1973-04-01), de Koe
patent: 3757231 (1973-09-01), Faustini
patent: 3838345 (1974-09-01), Schneider
patent: 3953838 (1976-04-01), Gilberg et al.
patent: 4058773 (1977-11-01), Clark et al.
patent: 4156288 (1979-05-01), Spandorfer
patent: 4679213 (1987-07-01), Sutherland
patent: 4837740 (1989-06-01), Sutherland
patent: 5036489 (1991-07-01), Theobald
patent: 5157633 (1992-10-01), Aoki
patent: 5179688 (1993-01-01), Brown et al.
"Micropipelines" by Ivan E. Sutherland, Communications of the ACM, vol. 32, No. 6, Jun. 1989, pp. 720-738.
Introduction to VLSI Systems by Carver Mead et al., "System Timing" by Charles Seitz, Chapter 7, pp. 258-261, Addison-Wesley Publishing Company, 1980.
"Modeling Timing Assumptions with Trace Theory" by Jerry R. Burch, 1989 IEEE, pp. 208-211.
"On the Models for Designing VLSI Asynchronous Digital Systems" by Tam-Anh Chu, Integration, The VlSI Journal 4 (1986), pp. 99-113.
Cirrus Logic Inc.
Dinh Son
Nelms David C.
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