Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1995-06-07
2001-02-13
Lane, Jack A. (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S209000
Reexamination Certificate
active
06189077
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The following coassigned patent applications are hereby incorporated herein by reference as background and supporting information to the subject matter disclosed herein:
Ser. No. 446,019, filed Dec. 5, 1989, “Data Communications System”;
Ser. No. 08/978,457, filed Nov. 19, 1992 and now abandoned, Ser. No. 798,278, filed Nov. 20, 1991 and now abandoned; a continuation of Ser. No. 408,454, filed Sep. 14, 1989, and now abandoned; a continuation of Ser. No. 256,803, filed Oct. 11, 1988 and now abandoned; a continuation of Ser. No. 821,375 filed Jan. 22, 1986 and now abandoned “Data Processing System with Variable Memory Bank Selection; and Japanese analog laid-open application No. 13275/1987;
Ser. No. 965,561 filed Oct. 23, 1992; a continuation of Ser. No. 426,480, filed Oct. 23, 1989, and now abandoned; a continuation of Ser. No. 346,388 filed Apr. 27, 1989 and now abandoned; a continuation of Ser. No. 207,034 filed Jun. 13, 1988 and now abandoned; a continuation of Ser. No. 821,641 filed Jan. 23, 1986 “Graphics Data Processor, A Data Processing System, A Graphics Processing System and a Method of Processing Graphics Data”;
U.S. Pat. No. 5,161,122, “Register Write Bit Protection Apparatus and Method”;
Ser. No. 387,569, filed Jul. 28, 1989 and now abandoned, “Graphics Display Split-Serial Register System”;
U.S. Pat. No. 5,329,617, “Graphics Processor Nonconfined Address Calculation System”;
Ser. No. 386,850, filed Jul. 28, 1989 and now abandoned, “Real Time and Slow Memory Access Mixed Bus Usage”;
U.S. Pat. No. 5,341,470, “Computer Graphics Systems, Palette Device and Methods for Shift Clock Pulse Insertion During Blanking”.
BACKGROUND OF THE INVENTION
Without limiting the general scope of the invention, its background is described in connection with computer graphics, as one example only.
In computer systems, a host computer can be programmed to perform general purpose tasks including graphics routines. Greater speed and additional features are often desirable, and so a graphics coprocessor is added to supplement the capabilities of the host computer.
The graphics coprocessor is also called a graphics system processor (GSP), examples of which are the Texas Instruments TMS34010 and TMS34020 GSPs. The addition of a graphics coprocessor makes the computer system a multiprocessor system which can benefit from advances in the art of multiprocessor technology. Also, different computer bus architectures are in use today such as the ISA and MCA architectures, and this situation complicates system and circuit definition. Furthermore, several different kinds of memory such as ROM, DRAM (dynamic random access memory) and VRAM (video RAM) are useful with computers that have graphics capability, and are desirably accommodated. A host computer may have one memory address space, which is an allocation of different memory addresses to different functions according to an address map, and the GSP may have another memory address space.
Any improvements in multiprocessor technology, memory and addressing management and other aspects relating to host computers and graphics system processors are desirable so that graphics and other computer and electronic systems can be made faster and more convenient in commercial application.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, a multifunction access circuit is provided for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit.
In general, another form of the invention is a multifunction access circuit with an address decoder having inputs from the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. A bank select circuit is responsive to addresses from the address bus of the second computer to supply a set of bank select outputs.
In general, a further form of the invention is a multifunction access circuit having a first address decoder with inputs for the address bus and a read line from the first computer. A second address decoder has inputs for the address bus and a write line from the second computer. A logic circuit is provided with a register selectable by either of the first address decoder and the second address decoder and having data outputs for connection to the data bus from the first computer, and having data inputs for connection to the data bus from the second computer.
Generally, still another form of the invention is a memory access circuit for use with a computer operative to assert read and write signals and an address. The circuit has a memory accessible by asserting addresses thereto, an address translator circuit having address inputs for the address supplied by the computer and outputs for supplying a translated address, and a logic circuit connected to the outputs of the address translator circuit and responsive to a write signal to automatically increment the translated address for the memory and responsive to a control signal to return to the translated address. Control circuitry connected to the logic circuit and responsive to a read signal from the computer supplies the control signal to the logic circuit to return to the translated address.
In general, a yet further form of the invention is a multifunction access circuit for use with first and second digital computers each having an address bus for addresses. The access circuit has an address translator circuit with address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers establishing predetermined address segments, and the address translator circuit is responsive to addresses on the address inputs in the address segments. Control logic circuitry is connected to said address translator circuit and operative to supply a control signal when the address at the address inputs changes from one segment to another segment.
In general, a still further form of the invention is a multifunction access circuit that has a register file having data inputs and outputs connected to the data bus for each of the first and second digital computers, and a pair of address decoders connected to the address bus for each of the first and second computers, the decoders connected to the register file to support simultaneous reads and writes.
Other circuits, devices, systems, and methods are described and claimed herein.
REFERENCES:
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4694426 (1987-09-01), Mason
patent: 4894797 (1990-01-01), Walp
patent: 4899352 (1990-02-01), Cucchi et al.
patent: 4968906 (1990-11-01), Pham et al.
patent: 5345419 (1994-09-01), Fenstermaker et al.
patent: 5371877 (199
Asal Michael D.
Littleton James G.
Nye Jeffrey L.
Robertson Iain C.
Short Graham B.
Brady III W. James
Lane Jack A.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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