Two channel computer bus architecture

Details Two channel computer bus architecture Two channel computer bus architecture

2005-01-21

2010-06-15

Patel, Niketa I (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S035000, C710S107000, C710S117000, C710S124000, C710S309000, C709S244000, C370S431000, C370S432000, C370S471000

Reexamination Certificate

active

07739425

ABSTRACT:
Various methods and processing systems are disclosed which include sending and receiving components communicating over a bus having first and second channels. The sending component may broadcast on the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data. The receiving component may store the write data broadcast on the first channel at the receiving component based on the write address locations and a first portion of the transfer qualifiers. The receiving component may also retrieve read data from the receiving component based on the read address locations and a second portion of the transfer qualifiers, and broadcast the retrieved read data on the second channel.

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