Two-bits per cell not-and-gate (NAND) nitride trap memory

Details Two-bits per cell not-and-gate (NAND) nitride trap memory Two-bits per cell not-and-gate (NAND) nitride trap memory

2008-06-13

2011-11-22

Ha, Nathan W (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27016

Reexamination Certificate

active

08063428

ABSTRACT:
A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region and the second source/drain region. A plurality of memory cells are disposed on the main surface above the well region. Each memory cell includes a first oxide layer formed on the main surface of the substrate, a charge storage layer disposed above the blocking oxide layer relative to the main surface of the semiconductor substrate and second oxide layer disposed above the charge storage layer relative to the main surface of the semiconductor substrate. A plurality of wordlines are disposed above the second oxide layer relative to the main surface of the semiconductor substrate.

REFERENCES:
patent: 5168334 (1992-12-01), Mitchell et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6181597 (2001-01-01), Nachumovsky
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6388293 (2002-05-01), Ogura et al.
patent: 6490196 (2002-12-01), Hsu et al.
patent: 6512263 (2003-01-01), Yuan et al.
patent: 6618286 (2003-09-01), Kato et al.
patent: 6624024 (2003-09-01), Prall et al.
patent: 6631088 (2003-10-01), Ogura et al.
patent: 6735118 (2004-05-01), Ogura et al.
patent: 6738291 (2004-05-01), Kamei et al.
patent: 6807105 (2004-10-01), Ogura et al.
patent: 6882001 (2005-04-01), Pascucci
patent: 6925007 (2005-08-01), Harari et al.
patent: 7050330 (2006-05-01), Forbes
patent: 7057940 (2006-06-01), Hsu et al.
patent: 7123518 (2006-10-01), Cheng et al.
patent: 7158420 (2007-01-01), Lung
patent: 7382659 (2008-06-01), Ogura et al.
patent: 7388252 (2008-06-01), Lung

Affiliated with

Also associated with

Rating

Two-bits per cell not-and-gate (NAND) nitride trap memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two-bits per cell not-and-gate (NAND) nitride trap memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two-bits per cell not-and-gate (NAND) nitride trap memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4295681