Two bits per cell non-volatile memory architecture

Details Two bits per cell non-volatile memory architecture Two bits per cell non-volatile memory architecture

2009-02-13

2011-12-20

Hidalgo, Fernando N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

C365S185290, C365S185030, C365S189160, C365S189150

Reexamination Certificate

active

08081521

ABSTRACT:
A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

REFERENCES:
patent: 6134140 (2000-10-01), Tanaka et al.
patent: 2005/0018519 (2005-01-01), Nii
patent: 2008/0247257 (2008-10-01), Brown

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