Two-bit semiconductor memory with enhanced carrier trapping

Details Two-bit semiconductor memory with enhanced carrier trapping Two-bit semiconductor memory with enhanced carrier trapping

2002-03-01

2004-06-15

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000, C257S327000, C257S329000, C257S345000, C257S411000, C438S216000, C438S261000, C438S421000, C438S591000, C438S595000

Reexamination Certificate

active

06750520

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory and a method of manufacture thereof and, more particularly, to a nonvolatile semiconductor memory capable of recording 2-bit information in one memory cell.
BACKGROUND ART
Recently, nonvolatile semiconductor memories capable of recording 2-bit information in one memory cell by changing a carrier injection position have been studied and developed. This nonvolatile semiconductor memory traps carriers in a charge trap film formed below the gate. The direction of a voltage applied between the source and the drain is reversed between write and read of information. Electrons are independently trapped in the charge trap film at positions corresponding to the two ends of the channel region. Two-bit information can be recorded depending on whether electrons are trapped at the two ends.
For example, WO 99/07000 discloses a nonvolatile semiconductor memory having the above structure. The structure and data write/read of the nonvolatile semiconductor memory disclosed in this reference will be briefly described with reference to FIG.
8
.
As shown in
FIG. 8
, a nonvolatile semiconductor memory
100
is constituted by a pair of diffused layers
102
and
103
functioning as a source/drain formed in a surface area of a p-type silicon semiconductor substrate
101
, a three-layered insulating film formed on the p-type silicon semiconductor substrate
101
between the diffused layers
102
and
103
, and a gate electrode
107
formed on the three-layered insulating film. The three-layered insulating film is made up from a gate insulating film (silicon oxide film)
104
, charge trap film (silicon nitride film)
105
, and silicon oxide film
106
.
The nonvolatile semiconductor memory
100
independently traps electrons at positions of the charge trap film that correspond to the two ends of the channel region. The nonvolatile semiconductor memory
100
can record a total of 2-bit information, one bit in RIGHT BIT and another bit LEFT BIT. Information is recorded by injecting electrons into the interface between the gate insulating film
104
and the charge trap film
105
. To record information in RIGHT BIT, electrons are injected into an area
109
shown in FIG.
8
. To record information in LEFT BIT, electrons are injected into an area
108
.
To write information in RIGHT BIT, e.g., the source and drain are respectively set at 0 V and about 5 V, generating a potential difference between the source and the drain. A high voltage (about 10 V) is applied to the gate
107
to form a channel
110
between the source and the drain. In a range l
2
where no channel
110
is formed, an electric field is generated by the potential difference between the source and the drain. In this range l
2
, channel hot electrons are generated, and electrons are trapped in the area
109
.
To read out information from RIGHT BIT, a voltage opposite in direction to the write voltage is applied between the source and the drain. Since electrons are trapped in the area
109
, no channel is formed from the diffused layer
103
to the diffused layer
102
below the area
109
, and the threshold increases. Thus, no current flows between the source and the drain. When no electron is trapped in the area
109
, a channel is formed between the source and the drain to flow a current. In this way, 1-bit information can be recorded in correspondence with whether electrons are trapped or not.
If a voltage in the same direction as that of the write voltage is applied in read while electrons are trapped in the area
109
, a channel is formed between the source and the drain, flowing a current. To prevent this, a voltage opposite in direction to the write voltage must be applied between the source and the drain in reading information.
Information can also be written in or read out from LEFT BIT similarly to RIGHT BIT by applying voltages opposite in direction to application voltages for write and read of information in RIGHT BIT.
For example, in writing information in RIGHT BIT, the injection position of channel hot electrons generated to increase the threshold of a memory cell in write varies depending on a voltage applied between the drain
103
and the gate electrode
107
. In the above-described conventional structure, electrons must be localized in the area
109
, but they are undesirably trapped in the gate insulating film
104
at the cannel center where they should not be injected.
Hot holes injected to decrease the threshold of a memory cell (erase operation) in a high-threshold state (e.g., write state) exhibit a generation mechanism different from that of hot electrons mentioned above. Their injection positions do not always coincide with each other. By repetitive write/erase, either type of charges may remain in the silicon nitride film
105
, resulting in a write/erase error.
This problem can be reduced by excessively injecting electrons to increase the threshold and excessively injecting holes to decrease the threshold. Excessive injection of carriers, however, decreases the write/erase speed and degrades the element performance. Excessive injection of carriers applies electrical stress more than necessary to an insulating film. This causes dielectric breakdown over time, which is undesirable in terms of element reliability.
Selecting a method of adjusting voltage application conditions in hole injection in relation to the distribution of the electron injection position does not optimize the hole generation efficiency. This also degrades element characteristics.
The present invention has been made to overcome these drawbacks, and has as its object to provide a semiconductor memory and a method of manufacture thereof that can reliably record and store 2-bit information, suppress generation of a write/erase error, and improve reliability in a semiconductor memory for recording 2-bit information by changing a carrier injection position.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a semiconductor memory comprising a pair of diffused layers formed in a surface area of a semiconductor substrate, and a gate electrode formed on a gate insulating film on the semiconductor substrate between the pair of diffused layers, wherein carriers are trapped in the gate insulating film by applying a predetermined voltage to the gate electrode, and the gate insulating film is formed higher in carrier trap characteristic at positions near the pair of diffused layers than in a remaining area.
According to the present invention, a method of manufacture of a semiconductor memory comprises the first step of sequentially forming first and second insulating films on a semiconductor substrate, the second step of selectively removing and patterning the first and second insulating films, the third step of forming a third insulating film on the semiconductor substrate in a predetermined range from the naked semiconductor substrate to a layer below the second insulating film, the fourth step of introducing impurities into the semiconductor substrate by using the second insulating film as a mask, thereby forming a pair of independent diffused layers in a surface area of the semiconductor substrate at two sides of the second insulating film, the fifth step of leaving the third insulating film formed in the predetermined range below the second insulating layer, and removing the third insulating film in a remaining area to expose the semiconductor substrate, the sixth step of thermally oxidizing the naked semiconductor substrate to form an element isolation film, the seventh step of removing the first and second insulating films to expose the underlying semiconductor substrate and third insulating film, and causing the third insulating film to function as a charge trap film, the eighth step of thermally oxidizing the naked surface of the semiconductor substrate to form a fourth insulating film, and covering upper and lower surfaces of the charge trap film with the fourth insulating film, the ninth step of forming a conductive film on the fourth insulating

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