Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-28
2003-06-17
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S319000, C257S321000
Reexamination Certificate
active
06580120
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to multi-bit semiconductor memory devices and more particularly to two-bit electrically erasable and programmable non-volatile memory devices. The present invention uses a trapping dielectric for charge retention.
BACKGROUND OF THE INVENTION
EEPROM (Electrically Erasable and Programmable Read Only Memory) offers the opportunity of electrically storing and removing data. The data stored in the EEPROM is represented by charge injected either onto a floating gate or into charge trapping sites in a dielectric or charge-trapping layer, forming part of a FET (Field Effect Transistor) structure comprised by the EEPROM. This electrical charge introduced in the FET structures influences the threshold voltage of at least a part of the FET structure. The charge, and hence the data associated with it, will be retained even when the electrical power to the memory is removed. Therefore these devices are also labeled as NVM (Non Volatile Memory) devices.
U.S. Pat. No. 5,969,383 entitled “Split gate memory device and method for accessing the same”, hereby incorporated by reference in its entirety, discloses a single bit EEPROM in which a split gate FET functions as a memory cell. Each memory cell contains a control gate (
32
) formed on top of an Oxide-Nitride-Oxide (ONO) stack (
25
) and, adjacent to but electrically insulated from this control gate (
32
), a select gate (
16
) on top of a dielectric (
14
). Source (
36
) and drain (
22
) regions are formed self-aligned respectively to this control gate and the select gate. The programming of the memory cell is done by the so-called source-side-injection (SSI) mechanism. The select gate is biased to form a conductive channel in the semiconductor region (
38
) underneath the select gate dielectric (
14
) to conduct electrons from the drain region onwards. The control gate is biased to have the corresponding underlying semiconductor region depleted and to attract the charge carriers, originating from the drain region, in the conductive channel. The attracted carriers are injected into and stored on the ONO stack (
24
) underneath the control gate (
32
). Reading and writing of the memory cell are done in opposite directions to obtain high read-out sensitivity.
PCT application WO0990700 entitled “Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping”, hereby incorporated by reference in its entirety, discloses a dual bit flash EEPROM, in which a single FET functions as a memory cell. Each memory cell contains a gate stack formed by a conductive layer (
24
) on top of a dielectric sandwich and source (
14
)/drain (
16
) regions formed self-aligned to this gate stack. The middle dielectric layer (
20
) of this dielectric sandwich acts as a charge-trapping layer. Within this charge-trapping layer, charge can be stored at two opposite sides, respectively at the source and at the drain side, instead of being distributed along the charge-trapping layer, as was the case in U.S. Pat. No. 5,969,383. Each side corresponds to a single bit of data, leading to two charge storage points under a single word line (
24
). An Oxide-Nitride-Oxide (ONO) stack can be used as such dielectric sandwich. The non-conductive nitride prevents, depending on its dimensions and process-conditions, the exchange of charge being stored at two opposite charge storage points present in the nitride layer. The programming of each bit of the two-bit memory cell is done by the so-called channel hot electron (CHE) injection. Reading and writing of the memory cell are also done in opposite directions or in an asymmetrical way
In “Twin MONOS cell with dual control gates”, published in the proceedings of the “VLSI Symposium” 2000, hereby incorporated by reference in its entirety, Hayashi et al. disclose a EEPROM memory cell consisting of two MONOS memory elements. Each memory element shares one common word or select gate (WG) with its neighbouring memory element. Each memory element further contains a control gate (CG) and a diffusion line (D). Two neighbouring memory cells will have the control gate and the diffusion line in common. The cross-sectional view of a “Twin MONOS”—memory cell very much resembles the “split gate” memory cell of U.S. Pat. No. 5,969,3 83 in that on both sides of the select gate (
16
) a control gate (
32
) is formed. Both source (
36
) and drain (
22
) regions are then formed self-aligned to their corresponding control gates (
32
,
35
). Each memory element is capable of storing a single bit of data. The programming of the memory element is done by the so-called source-side-injection (SSI) mechanism. Reading and writing of the memory cell are also done in opposite directions or in asymmetrical way.
Aims of the Invention
An aim, in an aspect of the invention, is to disclose a non-volatile memory structure and a method for accessing the memory structure that is power efficient and suitable for low-power applications.
Another aim, in an aspect of the invention, is to disclose a non-volatile memory structure that is simple and inexpensive to fabricate.
Yet another aim, in an aspect of the invention, is to disclose a non-volatile memory structure that is most area efficient.
Still another aim, in an aspect of the invention, is to disclose a non-volatile memory structure capable of storing at least two bits of data. Each bit of data can be multi-valued, i.e. a bit can have different charge contents, each charge content corresponding to a different data value.
Another aim, in an aspect of the invention, is to disclose a non-volatile memory structure that requires a reduced amount of charge to achieve a detectable change of threshold voltage.
SUMMARY OF THE INVENTION
In a first aspect of the invention a memory device and a method to manufacture this memory structure is disclosed. This method of forming a two-bit NVM EEPROM structure comprising the steps of:
defining a multitude of active area lines, separated by isolating field oxide regions;
depositing on top of these active area lines a first cell stack, comprising a first isolating dielectric, a dielectric capable of storing and retaining electric charge, a second isolating dielectric and a first conducting layer;
patterning the deposited first cell stack to form a multitude of lines at equidistant spacing and oriented substantially perpendicular to the active area lines, preferably the multitude of patterned first cell stacks comprises at least two lines;
filling the spacing in between the equidistant patterned first cell stacks with a second cell stack, comprising a first isolating dielectric, a dielectric capable of storing and retaining electric charge, an second isolating dielectric and a second conducting layer, the second cell stack being electrically insulated from the first cell stack;
planarizing the second cell stack thereby removing the second conducting layer outside the spacings between the equidistant patterned first cell stacks,
optionally forming self-aligned to the array of first and second cell stacks spacers and junctions, thereby defining a channel region underneath the array of abutted first and second cell stacks.
The memory structure according to the present invention is an array of 2-bit NVM memory cells comprising a first sequence of parallel isolated active area regions formed in a substrate, a second sequence of planar adjoining cell stacks, being positioned above and substantially perpendicular to said first sequence of parallel isolated active area regions, junctions formed self-aligned to and at opposite sides of said second sequence of planar adjoining cell stacks, said planar adjoining cell stacks being isolated from each other and comprising a conductive gate and a charge-storing dielectric layer, sandwiched between two dielectric layers, and comprising two regions, each region capable of storing 1 bit.
In a second aspect of the invention methods for programming, reading and erasing the memory structure according to the present invention are disclose
Interuniversitair Microelektronica Centrum (IMEC VZW)
McDonnell & Boehnen Hulbert & Berghoff
Meier Stephen D.
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