Two bit/four bit SONOS flash memory cell

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257SE29309, C257SE21423, C438S287000, C438S954000, C365S184000

Reexamination Certificate

active

07629640

ABSTRACT:
Charge migration in a SONOS memory cell is eliminated by physically separating nitride layer storage sites with dielectric material. Increased storage in a cell is realized with a double gate structure for controlling bit storage in line channels between a source and a drain, such as with a FinFET structure in which the gates are folded over the channels on sides of a fin.

REFERENCES:
patent: 6335554 (2002-01-01), Yoshikawa
patent: 6413802 (2002-07-01), Hu et al.
patent: 6720613 (2004-04-01), Chang
patent: 7091551 (2006-08-01), Anderson et al.
patent: 2003/0011020 (2003-01-01), Eitan
patent: 2004/0021172 (2004-02-01), Zheng et al.
patent: 2004/0119108 (2004-06-01), Chang
patent: 2004/0135195 (2004-07-01), Ahn et al.
patent: 2004/0235300 (2004-11-01), Mathew et al.
patent: 2004/0251487 (2004-12-01), Wu et al.
patent: 2005/0104117 (2005-05-01), Mikolajick et al.
patent: 2005/0199913 (2005-09-01), Hofmann et al.
patent: WO2004023556 (2004-03-01), None
Eitan et al, “NROM: A Novel Localized Trapping , 2-Bit Nonvolatile Memory Cell”, IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
Huang et al., “Sub-50 nm P-Channel FinFET”, IEEE Transaction on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.

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