Two-bit charge trap nonvolatile memory device and methods of...

Details Two-bit charge trap nonvolatile memory device and methods of... Two-bit charge trap nonvolatile memory device and methods of...

2005-11-22

2005-11-22

Tran, Andrew Q. (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S324000, C257S317000

Reexamination Certificate

active

06967373

ABSTRACT:
Two-bit programmable nonvolatile memory devices and methods of operating and fabricating the same are provided. The device comprises a plurality of device isolation layers, a plurality of word lines crossing over the device isolation layers, and a multiple insulation layer intervened between the word line and the active region. The multiple insulation layer includes a charge trap insulation layer. A source/drain region is formed at each region defined by adjacent word lines and the adjacent device isolation layers. The source/drain regions have the same surface area. A write operation of the device comprises applying a first level voltage, a ground voltage, and a write voltage to one bit line, another bit line, and a selected word line, thereby writing data into a charge trap insulation layer. By changing the voltages applied to the bit lines, 2 bits may be stored in one memory cell.

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patent: 5227326 (1993-07-01), Walker
patent: 6011725 (2000-01-01), Eitan
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Geppert, L., “The New Indelible Memories”, IEEE Spectrum, Mar. 2003, pp. 49-54.
Eitan B, et al.:“NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell.”In: IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, S. 543-545.

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