Twisted-pair driver with staggered differential drivers and glit

Electronic digital logic circuitry – Interface – Current driving

Patent

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Details

326 27, 326 29, 326 60, 326 83, 326 87, H03K 1716, H03K 17687, H03K 19003, H03K 190185

Patent

active

059173408

ABSTRACT:
A twisted-pair current driver is implemented in CMOS. EMI from sharp changes in the current driven is reduced by gradually changing the current driven when the inputs change. The current driver is divided into N differential drivers, each driving one-Nth of the total switching current to the twisted pair. Delay lines delay when input changes are sent to each of the four differential drivers, staggering their response. Either binary or multi-level-transition (MLT-3) data can be transmitted. A binary-to-MLT converter uses a dummy flip-flop to match delays and eliminate encoding glitches. Either the binary or the MLT-3 encoded data is coupled to the inputs of the delay lines and the differential drivers. The mid-level for MLT-3 is driven when both the inputs are high, causing the differential drivers to split the current among the two differential outputs to the twisted pair. The amount of current switched by each differential driver is doubled for multi-level mode to allow receivers to observe the smaller, multiple steps.

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