Twin EEPROM memory transistors with subsurface stepped...

Details Twin EEPROM memory transistors with subsurface stepped... Twin EEPROM memory transistors with subsurface stepped...

2006-02-14

2006-02-14

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000

Reexamination Certificate

active

06998670

ABSTRACT:
A memory array with memory cells arranged in rows and columns with each cell having twin EEPROMs featuring subsurface stepped floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate of each EEPROM and another portion being word lines. The twin EEPROMs share a common subsurface electrode by having diffused control lines and a diffused bit line. The two EEPROMs are symmetric across the common electrode.

REFERENCES:
patent: 4807188 (1989-02-01), Casagrande
patent: 5424233 (1995-06-01), Yang et al.
patent: 5917215 (1999-06-01), Chuang et al.
patent: 6043530 (2000-03-01), Chang
patent: 6323088 (2001-11-01), Gonzalez et al.
patent: 2002/0074583 (2002-06-01), Sugiyama et al.

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