Static information storage and retrieval – Read/write circuit – Including signal clamping
Reexamination Certificate
2000-10-31
2001-08-07
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal clamping
C365S203000, C365S205000, C365S207000
Reexamination Certificate
active
06272054
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to random access memory arrays, and more particular to a twin-cell, folded bitline memory architecture in which bitline crosstalk is essentially eliminated by combining a twin-cell, folded bitline layout with bitline shielding so that every other bitline of the array in sensed, while holding unselected bitlines which are adjacent to the sensed bitlines at a predetermined voltage level. The inventive architecture provides increased signal efficiency and improved test efficiency since the effects of data patterns are reduced.
BACKGROUND OF THE INVENTION
In the field of semiconductor memory devices such as DRAMs (dynamic random access memories) and EBBs (embedded memories), it is well known to use an array layout in which each bitline of the array is coupled to a sense amplifier. Such a layout is shown, for example, in FIG.
1
. Specifically,
FIG. 1
is a schematic diagram of a prior art single-cell, folded bitline memory layout which includes memory cells
10
, horizontally arranged wordlines WL
1
, WL
2
, WL
3
, WL
4
and etc, vertically arranged bitlines BL
1
, BL
2
, BL
3
, BL
4
and etc, transistors
12
, and sense amplifiers, SA
1
and SA
2
.
In the prior art single-cell, folded bitline memory layout shown in
FIG. 1
, each neighboring bitline, which forms a bitline pair, is coupled to a single sense amplifier. For example, BL
1
and BL
2
are both directly coupled to sense amplifier, SA
1
, whereas BL
3
and BL
4
are both directly coupled to sense amplifier SA
2
. Thus, each sense amplifier is capable of sensing only two bitlines in the single-cell arrangement shown in FIG.
1
.
In a read operation, the bitlines are electrically connected to the sense amplifier through transistors
12
and are subjected to amplification. Through amplification, each pair of bitlines, which have been precharged to predetermined levels, are changed to different potentials. Particularly, one of each pair of bitlines is discharged to the ground potential. Since the bitlines are arranged in parallel, a stray capacitance is present between two adjacent bitlines. Therefore, a change in potential at one bitline will affect the adjacent bitline as noise through the stray capacitance.
Twin-cell, folded bitline memory arrays which generate twice as much signal as a single-cell memory array are also known. A typical twin-cell, folded bitline memory array is shown in FIG.
2
. Specifically, the twin-cell memory array of
FIG. 2
comprises memory cells
10
, horizontally arranged wordlines WL
A
, WL
B
, and etc, and vertically arranged bitlines BL
1
, BL
2
, BL
3
, BL
4
and etc, transistors
12
and sense amplifiers, SA
1
and SA
2
. In the twin-cell memory layout shown in
FIG. 2
, WL
A
includes a pair of wordlines, e.g., WL
1
and WL
2
that are shorted together, whereas WL
B
denotes another pair of wordlines, e.g., WL
3
and WL
4
, that are shorted together. In the prior art twin-cell memory structure of
FIG. 2
, it is required that a pair of wordlines, i.e., WL
1
+WL
2
or WL
3
+WL
4
, be activated at the same time.
As in the case with single-cell layouts, prior art twin-cell layouts of the type illustrated in
FIG. 2
exhibit bitline line-to-line coupling which causes noise problems. In view of the drawbacks with conventional single- and twin-cell, folded bitline memory layouts, there is a need for a new and improved twin-cell, folded bitline memory design in which bitline crosstalk caused by bitline line-to-line coupling has been essentially eliminated.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a twin-cell, folded bitline memory layout in which crosstalk between adjacent bitlines has been essentially eliminated.
Another object of the present invention is to provide a twin-cell, folded bitline memory layout wherein the sense amplifiers can be laid-out at twice the pitch as compared to a conventional memory cell array. This is important since it creates more room for the sense amplifier drivers, which in turn, promotes a more efficient memory array.
A further object of the present invention is to provide a twin-cell, folded bitline layout which works at lower operating voltages than heretofore possible for conventional single- and twin-cell, folded bitline memory layouts.
These and other objects and advantages can be obtained in the present invention by combining a twin-cell, folded bitline layout with bitline shielding so that every other bitline of the array is sensed, while holding unselected bitlines of the array that are adjacent to the sensed bitlines at a constant predetermined voltage, i.e., potential, level.
Specifically, the present invention relates to a twin-cell, folded bitline memory array which comprises:
a plurality of bitlines arranged in one direction in parallel with each other, with every other bitline constituting a bitline pair;
a plurality of sense amplifiers being arranged in a line, wherein each sense amplifier is interconnected to two adjacent bitline pairs;
a plurality of wordlines arranged in a direction intersecting said plurality of bitlines, wherein a single wordline is coupled to every other bitline; and
isolation means located on said plurality of bitlines, said isolation means being arranged such that when every other bitline of said plurality of bitlines is being sensed, the adjacent bitlines of said plurality of bitlines are held at a predetermined potential by a clamping means.
It is noted that the isolation means together with the clamping means employed in the present invention provides bitline shielding by sensing every other bitline, while holding the unselected bitlines at a predetermined potential level. In an embodiment of the present invention, the isolation means includes a first isolation transistor formed on every other bitline of the array and a second isolation transistor in a parallel arrangement with the first isolation transistor formed on the adjacent bitlines of the array which do not include the first isolation transistor.
The first and second isolation transistors include associated clamping means. The clamping means employed in the present invention serve both as precharging means and as a clamp. In accordance to the present invention, each isolation transistor includes clamping means arranged in such a manner which makes it possible to clamp an adjacent bitline that is not being sensed at a constant predetermined voltage level. Thus, permitting the sensing of every other bitline of the array, while holding, i.e., clamping, the unselected bitlines at a constant predetermined potential level.
In the present twin-cell, folded bitline memory design, half of the wordlines are coupled to a first pair of bitlines, and the other half are coupled to a second pair of bitlines. Moreover, in the inventive twin-cell, folded bitline only one wordline needs to be activated.
The present invention also is directed to a method of substantially eliminating bitline crosstalk in a twin-cell, folded bitline memory array. Specifically, the method of the present invention comprises:
(a) providing a twin-cell, folded bitline memory array which comprises a plurality of bitlines arranged in one direction in parallel with each other, with every other bitline constituting a bitline pair; a plurality of sense amplifiers being arranged in a line, wherein each sense amplifier is interconnected to two adjacent bitline pairs; a plurality of wordlines arranged in a direction intersecting said plurality of bitlines, wherein a single wordline is coupled to every other bitline; and isolation means located on said plurality of bitlines, said isolation means being arranged such that when every other bitline of said plurality of bitlines is being sensed, the adjacent bitlines of said plurality of bitlines are held at a predetermined potential by clamping means; and
(b) switching on every other isolation means so as to activate every other bitline of said array, while holding other bitlines of said bitline pair not sensed at said predetermined voltage level with said clamping means.
Barth, Jr. John E.
Fifield John Atkinson
Capella, Esq. Steven
International Business Machines - Corporation
Lam David
Nelms David
Scully Scott Murphy & Presser
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