Twin-cell bit line sensing configuration

Details Twin-cell bit line sensing configuration Twin-cell bit line sensing configuration

2007-02-13

2007-02-13

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S190000

Reexamination Certificate

active

10992826

ABSTRACT:
Twin-cell bit line sensing structures and techniques are provided. Utilizing a folded bit line like structure, with bit line and complementary bit lines located together, sense amplifiers can be between cell arrays. Bit line switches, responsive to activated word lines in an array, may be used to selectively couple bit line pairs of the shared arrays with the sense amplifiers with a single word line activation.

REFERENCES:
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patent: 6898110 (2005-05-01), Ishimatsu et al.
patent: 6914837 (2005-07-01), Schroeder et al.
patent: 6947344 (2005-09-01), Suh
patent: 2002/0057601 (2002-05-01), Sakamoto et al.
patent: 2002/0141228 (2002-10-01), Fujino
patent: 2004/0017705 (2004-01-01), Hasegawa et al.
patent: 2004/0170075 (2004-09-01), Suh
PCT International Search Report and Written Opinion dated Mar. 23, 2006 for PCT/EP2005/012335.

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