Twin bit cell flash memory device

Details Twin bit cell flash memory device Twin bit cell flash memory device

2002-05-21

2004-01-06

Le, D. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000, C257S217000, C438S300000, C438S304000

Reexamination Certificate

active

06674133

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention provides a twin bit cell flash memory device and its fabricating method.
2. Description of the Prior Art
A read only memory (ROM) device, comprising a plurality of memory cells, is a semiconductor device with a primary function of memory storage. The ROM device is widely used in computer data storage and memory. Depending on the method of storing data, the ROM can be divided into several types such as Mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and electrically erasable programmable ROM (EEPROM).
Differing from other types of ROM that use a polysilicon or metal floating gate, a nitride read only memory (NROM) uses an insulating dielectric layer as a charge-trapping medium. Due to a highly-compacted nature of the silicon nitride layer, hot electrons tunneling from the MOS transistor into the silicon nitride layer are trapped to form an unequal concentration distribution so as to increase data reading speed and avoid current leakage.
Please refer to
FIG. 1
to
FIG. 4
of schematic diagrams of a prior art method for fabricating an NROM. As shown in
FIG. 1
, according to the prior art for fabricating a gate of the NROM, a semiconductor wafer
10
comprising a P-type silicon
12
is first provided. An oxidation process within a temperature range of 750° C.~1000° C. is then performed, to form an oxide layer with a thickness of 50-150 angstroms as a bottom oxide layer
14
on a surface of the silicon substrate
12
. Low-pressure chemical vapor deposition (LPCVD) is used to deposit a silicon nitride layer
16
with a thickness of 20 to 150 angstroms on the bottom oxide layer
14
, which functions as a charge trapping layer. Finally, an annealing process is performed under a high temperature of 950°C. for a duration of 30 minutes to repair the structure of the silicon nitride layer
16
. Water and steam are injected to perform a wet oxidation process to form a silicon oxy-nitride layer with a thickness of 50 to 150 angstroms as a top oxide layer
18
. The bottom oxide layer
14
, the silicon nitride layer
16
and the top oxide layer
18
comprise an ONO layer
20
on the surface of the silicon substrate
12
.
Please refer to
FIG. 2
of a photoresist layer
22
formed on a surface of the ONO layer
20
, and a photolithographic and etching process performed to form patterns in the photoresist layer
22
for defining the position of a bit line. Following that, the patterns of the photoresist layer
22
are used as a mask for performing a dry etching process to remove the top oxide layer
18
and the silicon oxide layer
16
which are not covered by the photoresist layer
22
, and to etch portions of the bottom oxide layer
14
to a predetermined depth. An arsenic (As) ion implantation process is performed with an ion concentration of 2~4×10
15
/cm
2
and with an energy of 50 Kev for forming a plurality of doped areas in the silicon substrate
12
, which function as bit lines
24
, i.e. buried drains of the memory device. Thereafter, the photoresist layer
22
is completely removed.
As
FIG. 3
shows, a thermal oxidation process is used to form a field oxide layer
26
on a top surface of bit lines
24
for separating each silicon oxide layer
16
and simultaneously to activate the dopants in each bit line
24
. Finally, as
FIG. 4
shows, a polysilicon layer or a polysilicide layer is deposited on the surface of the ONO layer
20
that functions as a word line
28
.
Since an NROM uses the charge trapping layer as a charge storage medium, hot electrons injected in the charge trapping layer during programming of the device form a distribution curve with respect to injection energy. Therefore, electron secondary injection easily occurs to form an electron tail and wider charge distribution. When an erasing process is performed, the distribution curve of electric holes injected into the charge trapping layer cannot completely overlap the distribution curve of injected electrons, leading to an incomplete erasure or longer erasing time.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a structure of a twin bit cell flash memory device for increasing memory cell density and to solve the problem of incomplete erasure that occurs in the NROM of the prior art.
It is another object of the present invention to provide a method for fabricating a flash memory device so as to fabricate a twin bit cell flash memory device with high integration. As well, the problem of incomplete erasure of NROM is prevented and reliability of data retention is improved.
In an embodiment of the present invention, the method comprises firstly forming a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si
1−x
Ge
x
, x=0.05~1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.
The present invention uses a conductive layer as a charge trapping layer and uses an oxidation region to separate the charge trapping layer into two isolated charge capture regions. Hence, the two regions can be respectively read and be programmed to form a twin bit cell structure. Additionally, the two charge capture regions are both conductive layers comprising poly silicon germanium, so the combination efficiency of electrons and electric holes is very high in the conductive layer. Therefore, the problem of incomplete erasure of NROM is prevented and reliability of data retention is improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 6538292 (2003-03-01), Chang et al.

Affiliated with

Also associated with

Rating

Twin bit cell flash memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Twin bit cell flash memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Twin bit cell flash memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3257514