Twin bit cell flash memory device

Details Twin bit cell flash memory device Twin bit cell flash memory device

2001-03-29

2003-03-25

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000, C257S368000, C438S217000, C438S276000, C438S289000

Reexamination Certificate

active

06538292

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a flash memory cell, and more particularly, to a method of fabricating a flash memory cell having a self-aligned floating gate structure and enhanced coupling ratio characteristics.
2. Description of the Prior Art
A read only memory (ROM) device, comprising a plurality of memory cells, is a semiconductor device with a primary function as memory storage. The ROM device is widely used in computer data storage and memory. Depending on the method of storing data, the ROM can be divided into several types such as mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and electrically erasable programmable ROM (EEPROM).
Differing from other types of ROMs that use a polysilicon or metal floating gate, a nitride read only memory (NROM) uses an insulating dielectric layer as a charge-trapping medium. Due to the highly-compacted nature of the silicon nitride layer, hot electrons tunneling from the MOS transistor into the silicon nitride layer are trapped to form an unequal concentration distribution so as to increase data reading speeds and avoid current leakage.
Please refer to
FIG. 1
to FIG.
4
.
FIG. 1
to
FIG. 4
are schematic diagrams of a prior art method for fabricating an NROM. As shown in
FIG. 1
, according to the prior art for fabricating a gate of the NROM, a semiconductor wafer
10
comprising a P-type silicon
12
is first provided. A low temperature oxidation process within a temperature range of 750° C.~1000° C. is then performed, to form an oxide layer with a thickness of 50-150 angstroms as a bottom oxide layer
14
on the surface of the silicon substrate
12
.Low-pressure chemical vapor deposition (LPCVD) is used to deposit a silicon nitride layer
16
with a thickness of 20-150 angstroms on the bottom oxide layer
14
, which functions as a charge trapping layer. Finally, an annealing process is performed under a high temperature of 950° C. for a duration of 30 minutes to repair the structure of the silicon nitride layer
16
. Water steam is injected to perform a wet oxidation process to form a silicon oxy-nitride layer with a thickness of 50 to 150 angstroms as a top oxide layer
18
. The bottom oxide layer
14
, the silicon nitride layer
16
and the top oxide layer
18
comprise an ONO dielectric structure
20
on the surface of the silicon substrate
12
.
Please refer to FIG.
2
.
FIG.2
shows a photoresist layer
22
formed on the surface of the ONO dielectric structure
20
, and a photolithographic and etching process performed to form patterns in the photoresist layer
22
for defining the position of a bit line. Following that, the patterns of the photoresist layer
22
are used as a mask for performing a dry etching process to remove the top oxide layer
18
and the silicon oxide layer
16
which are not covered by the photoresist layer
22
, and to etch portions of the bottom oxide layer
14
to a predetermined depth. An arsenic (As) ion implantation process is performed with an ion concentration of 2~4×10
15
/cm
2
and with an energy of 50 Kev for forming a plurality of doped areas in the silicon substrate
12
, which function as bit lines
24
, i.e. buried drains of the memory device. Thereafter, the photoresist layer
22
is completely removed.
As
FIG. 3
shows, a thermal oxidation process is used to form a field oxide layer
26
on the top surface of bit lines
24
for separating each silicon oxide layer
16
and simultaneously to activate the dopants in each bit line
24
. Finally, as
FIG. 4
shows, a polysililcon layer or a polysilicide layer is deposited on the surface of the ONO dielectric structure
20
that functions as a word line
28
.
Since an NROM uses the charge trapping layer as a charge storage medium, hot electrons injected in the charge trapping layer during programming of the device will form a distribution curve with respect to injection energy. When an erasing process is performed, electric holes must be injected into the charge trapping layer to neutralize the electron charges stored in the charge trapping layer. However, the mass of an electron differs greatly from that of the electric hole. Therefore the distribution curve of electric holes injected into the charge trapping layer cannot completely overlap the distribution curve of injected electrons, leading to an incomplete erasure.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a structure of a twin bit cell flash memory device and to solve the problem of incomplete erasure that occurs in the NROM of the prior art.
The present invention provides a twin bit cell flash memory device. The memory device is positioned on the surface of a semiconductor wafer. The semiconductor wafer comprises a semiconductor substrate of a first conductive type, a source and a drain of a second conductive type, each positioned in a respective predetermined area of the semiconductor substrate, and a channel positioned on the surface of the semiconductor substrate between the source and the drain. The memory device contains a first dielectric layer covering the surface of the channel, a conductive layer formed and covering the surface of the first dielectric layer and the conductive layer containing another insulating region for separating the conductive layer so as to form two isolated conductive regions. The memory device also contains a second dielectric layer formed and covering the surface of the conductive layer, and a gate formed and covering the surface of the second dielectric layer. The two conductive regions are used as a charge trapping layer to receive and hold electrons injected into the conductive region, so forming a twin bit cell flash memory device.
The present invention uses a conductive layer as a charge trapping layer and uses an oxidation region to separate the charge trapping layer into two isolated charge capture regions. Hence, the two regions can be respectively read and be programmed so as to form a twin bit cell structure. Additionally, the stored electrons can distribute uniformly in the conductive layer, therefore preventing the problem of incomplete erasure of NROM according as suffered in the prior art.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5185646 (1993-02-01), Mizuno
patent: 5483487 (1996-01-01), Sung-Mu
patent: 6051470 (2000-04-01), An et al.

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