Turbo LDPC decoding

Details Turbo LDPC decoding Turbo LDPC decoding

2011-04-26

2011-04-26

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

Reexamination Certificate

active

07934147

ABSTRACT:
An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.

REFERENCES:
patent: 3703705 (1972-11-01), Patel
patent: 3745526 (1973-07-01), Hong et al.
patent: 5425038 (1995-06-01), Chen
patent: 6715121 (2004-03-01), Laurent
patent: 7178080 (2007-02-01), Hocevar
patent: 7246304 (2007-07-01), Kim
patent: 7395490 (2008-07-01), Richardson et al.
patent: 7502987 (2009-03-01), Kyung et al.
patent: 7653867 (2010-01-01), Stankovic et al.
patent: 2007/0043998 (2007-02-01), Lakkis
patent: 2008/0263425 (2008-10-01), Lakkis
patent: 2007019187 (2007-02-01), None
International Preliminary Report on Patentability- PCT/US2006/030145, The International Bureau of WIPO- Geneva, Switzerland.
Written Opinion- PCT/US2006/030145, International Search Authority- US, Jul. 12, 2007.
International Search Report- PCT/US2006/030145, International Search Authority- US, Jul. 12, 2007.
M. Mansour et al., “High-Throughput LDPC Decoders,” IEEE Transactions on Very Large Scale Integrations systems, vol. 11, No. 6, Dec. 2003.
Guilloud, “Architecture generique de decodeur de codes LDPC,” Jul. 2, 2004, These Presentee Pour Obtenir Le Grade de Docteur de L'Ecolenational Superieure Des Telecommunications. XP002370625.
Richardson, et al., “Efficient Encoding of Low-Density Parity-Check Codes,” Feb. 1, 2001, IEEE Transactions on Information Theory, US, XP011027880.
Sha, et al., “Efficient Decoder Implementation for QC-LDPC Codes,” Jun. 1, 2006, Communications, Circuits and Systems Proceedings, 2006 International Conference on, IEEE, PI, pp. 2498-2502, XP031010935.
Yadav, et al., “Design and Implementation of LDPC Codes for DVB-S2,”, 2005, Conf. record of the 39th Asilomar Conf. on Signals, Systems and Computers, Oct. 28-Nov. 1, 2005, USA, pp. 723-728, XP010900097.
International Search Report—PCT/US09/046175. International Searching Authority—European Patent Office, Oct. 8, 2009.
Written Opinion—PCT/US09/046175, International Searching Authority—European Patent Office, Oct. 8, 2009.
Min-Seok Oh et al., Scalable LDPC coding for OFDMA, Aug. 13, 2004, IEEE 802.16 Broadband wireless access working group, <http://ieee 802.org/16> retreived from google.com on Mar. 9, 2010 pp. 1-10.

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