Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-09-01
2003-09-23
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S780000
Reexamination Certificate
active
06625778
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a turbo error-correcting decoding method and apparatus in a communications field, such as radio communications apparatus, and more particularly to a turbo error-correcting decoding method and apparatus capable of performing calculation on soft-decision information at high speed.
2. Description of the Related Art
FIG. 10
is a block diagram showing the configuration of a conventional turbo error-correcting decoder disclosed in “Soft-Output Decoding Algorithms in Interactive Decoding of Turbo Codes (D. Divsalar and F. Pollara, Feb. 15, 1996) on page 63-87 of TDA Progress Report.
In
FIG. 10
, designated
100
is a turbo error-correcting decoder. Denoted
101
is a calculation means which calculates an average value and a variance value of reliability information on received bits (absolute value of soft-decision information) and which, based on these values, determines a value by which to convert the soft-decision information and multiplies each soft-decision information with the value. Reference number
102
represents a first addition means which adds up the output result of the calculation means
101
and the previous soft-decision output result. Reference number
103
denotes a first memory means which stores the result of the first addition means
102
. Denoted
104
is a first soft-decision information calculation means which calculates the soft-decision information from the output of the calculation means
101
and the output of the first addition means
102
. Denoted
105
is a first subtraction means which calculates a soft-decision output result, a difference between the result of the first addition means
102
stored in the first memory means
103
and the soft-decision information calculated by the first soft-decision information calculation means
104
.
Designated
106
is a second addition means for adding up the output result of the calculation means
101
and the output result of the first subtraction means
105
. Denoted
107
is a second memory means to store the result of the second addition means
106
. Denoted
108
is an interleaver to rearrange the order of data. Designated
109
is a second soft-decision information calculation means which calculates the soft-decision information from the output of the interleaver
108
and the output of the calculation means
101
. Reference number
110
denotes a deinterleaver which reinstates the order of data rearranged by the interleaver
108
. Reference number
111
denotes a second subtraction means which calculates a soft-decision output result, a difference between the result of the second addition means
106
stored in the second memory means
107
and the soft-decision information calculated by the second soft-decision information calculation means
109
. Designated
112
is a hard-decision generation means to generate hard-decision information.
Next, the configuration of a general turbo code encoder will be explained.
FIG. 11
is a block diagram showing a conventional turbo code encoder. This diagram defines a first sequence, a second sequence and a third sequence.
In
FIG. 11
, denoted
120
is a turbo code encoder.
121
and
122
represent a first feedback type convolutional encoder and a second feedback type convolutional encoder, respectively, for generating code sequences.
123
represents an interleaver. In the following explanation, a data bit sequence output as is and its reception sequence are called a first sequence; a sequence generated by the first feedback type convolutional encoder
121
and its reception sequence are called a second sequence; and a sequence generated by the second feedback type convolutional encoder
122
and the interleaver
123
and its reception sequence are called a third sequence.
Next, the operation of the turbo error-correcting decoder
100
when it receives transmission bits encoded by the turbo code encoder
120
will be explained by referring to FIG.
10
.
First, the turbo code encoder
120
sends transmission sequence bits of the first, second and third sequences through communication channel or radio, and they are received by the turbo error-correcting decoder
100
.
In the decoder
100
, upon receiving the reception bits of the first, second and third sequences, the calculation means
101
calculates an average value A and a variance value &sgr;
2
of the reliability information on the received bits. Based on these values, it calculates 2A/&sgr;
2
and multiplies each of the input soft-decision information by the calculated value of 2A/&sgr;
2
.
Next, the multiplied result of the calculation means
101
is sent to the first addition means
102
which adds up the soft-decision output results of second subtraction means
111
and the first sequence among the soft-decision information calculated by the calculation means
101
. At the first decoding, the soft-decision output result produced by the second subtraction means
111
is 0, so the first addition means
102
outputs the result of the calculation means
101
as is.
The added result of the first addition means
102
is sent to the first memory means
103
where it is stored. The added result is also entered into the first soft-decision information calculation means
104
, which calculates and outputs the soft-decision information of the decoded first sequence on the basis of the reliability information on the second sequence corrected by the calculation means
101
by using a soft-decision decoding algorithm such as MAP decoding or log-MAP decoding.
Next, the first subtraction means
105
subtracts the value stored in the first memory means.
103
from the soft-decision information provided by the first soft-decision information calculation means
104
and outputs the calculated difference as the soft-decision output result.
Next, the calculated result from the calculation means
101
is sent to the second addition means
106
, which adds up the soft-decision information of the first sequence calculated by the calculation means
101
and the soft-decision output result produced by the first subtraction means
105
.
The added result of the second addition means
106
is supplied to the second memory means
107
where it is stored. The added result of the second addition means
106
is also supplied to the interleaver
108
where the order of the calculated result is changed. Then, the output of the interleaver
108
is entered into the second soft-decision information calculation means
109
, which calculates and outputs the soft-decision information of the decoded first sequence on the basis of the soft-decision information of the third sequence corrected by the calculation means
101
by using the soft-decision decoding algorithm such as MAP decoding or log-MAP decoding.
Next, the deinterleaver
110
restores the original order of the data. Then, the second subtraction means
111
subtracts the value stored in the second memory means
107
from the soft-decision information output from and deinterleaved by the deinterleaver
110
to calculate a difference or soft-decision output result.
When the above process has been repeated a predetermined number of times, the hard-decision means
112
makes a hard-decision on whether the value output from the deinterleaver
110
is 0 or 1, and outputs the decision as a decoding result. The counting of the number of repetitions and the control for inputting the value into the hard-decision means
112
are performed by a control means (not shown).
In the conventional turbo error-correcting decoder, because the decoding performance is raised for any receiving state, the soft-decision information needs to be corrected by using the average value and the variance value of after-reception reliability. This, however, requires calculating the average and variance values of reliability. This calculation is very complicated and poses problems of slowing down the processing speed and making circuits complex.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a turbo error-
Fujita Hachiro
Nakamura Takahiko
Yoshida Hideo
Birch & Stewart Kolasch & Birch, LLP
Chase Shelly A
De'cady Albert
Mitsubishi Denki & Kabushiki Kaisha
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