Turbo encoder with reduced processing delay

Details Turbo encoder with reduced processing delay Turbo encoder with reduced processing delay

2006-05-23

2006-05-23

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S786000, C714S702000

Reexamination Certificate

active

07051261

ABSTRACT:
A turbo encoder includes a memory for temporarily storing an incoming data sequence and an interleaved address generator (IAG) designed to generate a sequence of addresses corresponding to the interleaved data sequence. The IAG performs calculations based on the length of the incoming data sequence and is able to generate a first interleaved address by (or before) the time the incoming data sequence has completely shifted into the memory. As a result, the encoder begins to output encoded data substantially as soon as the corresponding incoming data have been received, thus substantially reducing the processing delay. In addition, each interleaved address can be generated on the fly as needed during data output. As a result, the entire set of interleaved addresses does not need to be stored, thus reducing the memory requirements for the encoder.

REFERENCES:
patent: 6353900 (2002-03-01), Sindhushayana et al.
patent: 6668343 (2003-12-01), Kim et al.
patent: 6854077 (2005-02-01), Chen et al.

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